UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 887

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C.2 Revision History of Preceding Editions
2nd edition
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
Edition
1.1 Features
• Change of status indication of
• Addition of On-chip BCD adjustment
• Addition of 8-bit resolution D/A converter
Addition of Caution 2 to 1.4 Pin Configuration (Top View)
Addition of 1.5 78K0R Microcontroller Lineup
Addition of BCD correction circuit and change of direction of arrow on external bus
interface I/O pins in 1.6 Block Diagram
Change of status indication of
1.7 Outline of Functions
Modification of alternate function of EX25, EX26, SO00, SO01, TxD0, and TxD3
functions in 2.1 (2) Non-port functions
Addition of alternate function description and modification of Caution in 2.2.5 P40 to
P47 (port 4)
Addition of I/O Circuit Type in Table 2-2 Connection of Unused Pins
Addition of Figure 2-1 Pin I/O Circuit List
Deletion of descriptions of CALLF instruction in CHAPTER 3
Modification of description in 3.1 Memory Space
Addition of Note in Figure 3-5 Memory Map (
Correspondence Between Data Memory and Addressing (
Addition of Note in Figure 3-7 Memory Map (
Correspondence Between Data Memory and Addressing (
Modification of description and addition of diagram example and explanation of PMC
register in 3.1.2 Mirror area
Change of reset value of Hour count register and Alarm hour register in Table 3-5
SFR List
Change of reset value of Day count register and Month count register in Table 3-5
SFR List
Change of reset value of Back ground event control register in Table 3-5 SFR List
Addition of BCD correction carry register and Note to Table 3-5 SFR List
Change of symbols of higher multiplication result storage register and lower
multiplication result storage register in Table 3-5 SFR List
Addition of Regulator mode control register and BCD adjust result register in Table 3-
6 Extended SFR (2nd SFR) List
Addition of SFR name for the lower 8 bits and modifications of R/W attribute and
manipulable bit range for registers SSRmn, SIRmn, SEm, SSm, STm, SPSm, SOEm,
SOLm, TCR0n, TSR0n, TE0, TS0, TT0, TPS0, TO0, TOE0, TOL0, and TOM0 in
Table 3-6 Extended SFR (2nd SFR) List
Change of reset value of Serial output register 0 and Serial output register 1 in Table
3-6 Extended SFR (2nd SFR) List
Change of reset value of Serial output enable register 0 and Serial output enable
register 1 in Table 3-6 Extended SFR (2nd SFR) List
Change of R/W attribute of Timer channel counter register 0n in Table 3-6 Extended
SFR (2nd SFR) List
Addition of 3.3 Instruction Address Addressing
Addition of 3.4 Addressing for Processing Data Addresses
APPENDIX C REVISION HISTORY
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User’s Manual U17893EJ8V0UD
Description
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PD78F1168) and Figure 3-15
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CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 1 OUTLINE
CHAPTER 2 PIN
FUNCTIONS
Chapter
(1/20)
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