UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 904

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

902
7th edition
Edition
Modification of Figure 12-44 Timing Chart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of transfer rate in 12.5.4 Slave transmission
Change of Figure 12-48 Procedure for Stopping Slave Transmission
Change of Figure 12-49 Procedure for Resuming Slave Transmission
Change of Figure 12-50 Timing Chart of Slave Transmission (in Single-
Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of Figure 12-52 Timing Chart of Slave Transmission (in Continuous
Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of Figure 12-53 Flowchart of Slave Transmission (in Continuous
Transmission Mode)
Change of transfer rate in 12.5.5 Slave reception
Change of (b) Serial output enable register m (SOEm) … Clears only the bits of
the target channel to 0. in Figure 12-54. Example of Contents of Registers for
Slave Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20)
Modification of Figure 12-58 Timing Chart of Slave Reception (in Single-
Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of transfer rate in 12.5.6 Slave transmission/reception
Change of Figure 12-62 Procedure for Stopping Slave Transmission/Reception
Change of Figure 12-63 Procedure for Resuming Slave Transmission/Reception
Modification of Figure 12-64 Timing Chart of Slave Transmission/Reception (in
Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Modification of Figure 12-66 Timing Chart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of Note in 12.5.7 Calculating transfer clock frequency
Change of Note 2 in Table 12-2 Selection of Operation Clock
Addition of Caution to 12.6 Operation of UART (UART0, UART1, UART2, UART3)
Communication
Change of Figure 12-70 Procedure for Stopping UART Transmission
Change of Figure 12-72 Timing Chart of UART Transmission (in Single-
Transmission Mode)
Change of Figure 12-74 Timing Chart of UART Transmission (in Continuous
Transmission Mode)
Change of 12.6.2 UART reception
Change of (b) Serial output enable register m (SOEm) in Figure 12-76 Example
of Contents of Registers for UART Reception of UART (UART0, UART1, UART2,
UART3)
Modification of Figure 12-80 Timing Chart of UART Reception
Modification of transfer data length in 12.6.3 LIN transmission
Change of Note 2 in Figure 12-82 Transmission Operation of LIN
Change of Note 2 in Table 12-3 Selection of Operation Clock
Addition of Note to 12.7 Operation of Simplified I
Addition of Note to 12.7.1 Address field transmission
Change of Figure 12-89 Initial Setting Procedure for Address Field
Transmission
Change of Figure 12-90 Timing Chart of Address Field Transmission
Addition of Note to 12.7.2 Data transmission
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
Description
2
C (IIC10, IIC20) Communication
CHAPTER 12 SERIAL
ARRAY UNIT
Chapter
(18/20)