UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 604

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3 Registers Controlling Interrupt Functions
to interrupt request sources.
602
INTWDTI
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTST3
INTSR3
INTSRE3
INTDMA0
INTDMA1
INTST0
INTCSI00
INTSR0
INTCSI01
INTSRE0
The following 6 types of registers are used to control the interrupt functions.
• Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
• Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
• Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
• External interrupt rising edge enable registers (EGP0, EGP1)
• External interrupt falling edge enable registers (EGN0, EGN1)
• Program status word (PSW)
Table 16-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding
Notes 1. Do not use UART0 and CSI00 at the same time because they share flags for the interrupt request
PR11H, PR12L, PR12H)
Interrupt
Source
Note 1
Note 2
Note 1
Note 2
2. Do not use UART0 and CSI01 at the same time because they share flags for the interrupt request
sources. If one of the interrupt sources INTST0 and INTCSI00 is generated, bit 5 of IF1H is set to 1. Bit
5 of MK0H, PR00H, and PR10H supports these two interrupt sources.
sources. If one of the interrupt sources INTSR0 and INTCSI01 is generated, bit 6 of IF0H is set to 1. Bit
6 of MK0H, PR00H, and PR10H supports these two interrupt sources.
WDTIIF
LVIIF
PIF0
PIF1
PIF2
PIF3
PIF4
PIF5
STIF3
SRIF3
SREIF3
DMAIF0
DMAIF1
STIF0
CSIIF00
SRIF0
CSIIF01
SREIF0
Table 16-2. Flags Corresponding to Interrupt Request Sources (1/2)
Interrupt Request Flag
Note 1
Note 2
Note 1
Note 2
CHAPTER 16 INTERRUPT FUNCTIONS
IF0L
IF0H
Register
User’s Manual U17893EJ8V0UD
WDTIMK
LVIMK
PMK0
PMK1
PMK2
PMK3
PMK4
PMK5
STMK3
SRMK3
SREMK3
DMAMK0
DMAMK1
STMK0
CSIMK00
SRMK0
CSIMK01
SREMK0
Interrupt Mask Flag
Note 1
Note 2
Note 1
Note 2
MK0L
MK0H
Register
WDTIPR0, WDTIPR1
LVIPR0, LVIPR1
PPR00, PPR10
PPR01, PPR11
PPR02, PPR12
PPR03, PPR13
PPR04, PPR14
PPR05, PPR15
STPR03, STPR13
SRPR03, SRPR13
SREPR03, SREPR13
DMAPR00, DMAPR10
DMAPR01, DMAPR11
STPR00, STPR10
CSIPR000, CSIPR100
SRPR00, SRPR10
CSIPR001, CSIPR101
SREPR00, SREPR10
Priority Specification Flag
Note 2
Note 1
Note 1
Note 2
PR00L,
PR10L
PR00H,
PR10H
Register