UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 903

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7th edition
Edition
Addition of 7.4.6 32.768 kHz output of real-time counter
Addition of 7.4.7 512 Hz, 16.384 kHz output of real-time counter
Addition of 7.4.8 Example of watch error correction of real-time counter
Change of Cautions 1 and 2 in Figure 8-2 Format of Watchdog Timer Enable
Register (WDTE)
Change of Caution 3 in Table 8-4 Setting Window Open Period of Watchdog
Timer
Change of description in 10.2 (9) AV
Change of Cautions in Figure 10-3 Format of Peripheral Enable Register 0
(PER0)
Change of Table 10-3 A/D Conversion Time Selection
Addition of Caution 4 to Figure 10-10 Format of A/D Port Configuration Register
(ADPC)
Addition of 10.5 Temperature Sensor Function (Expanded-Specification
Products (
Addition of 10.7 (2) Reducing current when A/D converter is stopped
Addition of 11.2 (1) AV
Change of Cautions in Figure 11-2. Format of Peripheral Enable Register 0
(PER0)
Addition of 11.3 (4) Port mode register 11 (PM11)
Change of description in 11.4.1 Operation in normal mode
Change of description in 11.4.2 Operation in real-time output mode
Addition of Note to 12.1.3 Simplified I
Change of Cautions in Figure 12-4. Format of Peripheral Enable Register 0
(PER0)
Change of Note 2 in Figure 12-5 Format of Serial Clock Select Register m
(SPSm)
Change of and addition of Note to Figure 12-7 Format of Serial Communication
Operation Setting Register mn (SCRmn)
Change of Cautions 1 in Figure 12-22. Peripheral Enable Register 0 (PER0)
Setting When Stopping the Operation by Units
Change of Figure 12-26 Procedure for Stopping Master Transmission
Change of Figure 12-27 Procedure for Resuming Master Transmission
Change of Figure 12-28 Timing Chart of Master Transmission (in Single-
Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of Figure 12-30 Timing Chart of Master Transmission (in Continuous
Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of (b) Serial output enable register m (SOEm) …Clears only the bits of
the target channel to 0. in Figure 12-32. Example of Contents of Registers for
Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20)
Modification of Figure 12-36 Timing Chart of Master Reception (in Single-
Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of Figure 12-40 Procedure for Stopping Master Transmission/Reception
Change of Figure 12-41 Procedure for Resuming Master
Transmission/Reception
Modification of Figure 12-42 Timing Chart of Master Transmission/Reception (in
Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
μ
PD78F115xA) Only)
REF1
pin
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
REF0
Description
2
C (IIC10, IIC20)
pin
CHAPTER 7 REAL-
TIME COUNTER
CHAPTER8
WATCHDOG TIMER
CHAPTER 10 A/D
CONVERTER
CHAPTER 11 D/A
CONVERTER
CHAPTER 12 SERIAL
ARRAY UNIT
Chapter
(17/20)
901