UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 891
UPD78F1152AGC-GAD-AX
Manufacturer Part Number
UPD78F1152AGC-GAD-AX
Description
MCU 16BIT 78K0R/KX3 80-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1152AGC-GAD-AX.pdf
(908 pages)
Specifications of UPD78F1152AGC-GAD-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1152AGC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2nd edition
Edition
Modification of description on f
Table 19-1 Operating Statuses in HALT Mode.
Modification of description in 19.1.2 (1) Oscillation stabilization time counter
status register (OSTC).
Change of reset value of 19.1.2 (2) Oscillation stabilization time select register
(OSTS).
Modification of setting in Figure 19-2. Format of Oscillation Stabilization Time
Select Register (OSTS).
Modification of description on f
in Table 19-2 Operating Statuses in STOP Mode.
Modification of Figure 19-5 Operation Timing When STOP Mode Is Released.
Modification of Figure 19-6 STOP Mode Release by Interrupt Request Generation
and addition of (2) When high-speed system clock (external clock input) is used
as CPU clock.
Addition of RESF register read signal to Figure 20-1 Block Diagram of Reset
Function.
Addition of external bus interface to Table 20-1 Operation Statuses During Reset
Period.
Modification of status after reset of hour count register (HOUR), day count register
(DAY), month count register (MONTH), and alarm minute register (ALARMWH) of
real-time counter in Table 20-2 Hardware Statuses After Reset Acknowledgment.
Modification and addition of Note 4 in Figure 21-2 Timing of Generation of Internal
Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector.
Addition of 22.4.1 When used as reset.
Addition of 22.4.2 When used as interrupt.
Addition of chapter.
Modification of Caution in Figure 24-2 Format of Option Byte (000C1H/010C1H).
Addition of 25.5 Registers that Control Flash Memory.
Addition of chapter.
Addition of chapter.
DC Characteristics
• Change of MIN. value and addition of Note 1 of input voltage, high (V
• Change of MAX. value of input voltage, low (V
• Change of MAX. value and addition of Note 2 of input voltage, low (V
• Change of condition of output voltage, high (V
• Change of condition of output voltage, low (V
• Change of condition of Input leakage current, high (I
• Change of condition of Input leakage current, low (I
Modification of figure of AC timing measurement position in AC Characteristics (1)
Basic operation
APPENDIX C REVISION HISTORY
IL
IL
of system clock and f
of system clock, RAM, and real-time counter (RTC)
User’s Manual U17893EJ8V0UD
Description
OL1
OH1
IL5
, V
)
)
OL3
LIL4
X
LIH4
, f
)
)
EX
)
of main system clock in
IL7
IH7
)
)
CHAPTER 19
STANDBY FUNCTION
CHAPTER 20 RESET
FUNCTION
CHAPTER 21 POWER-
ON-CLEAR CIRCUIT
CHAPTER 22 LOW-
VOLTAGE DETECTOR
CHAPTER 23
REGULATOR
CHAPTER 24 OPTION
BYTE
CHAPTER 25 FLASH
MEMORY
CHAPTER 26 BCD
CORRECTION
CIRCUIT
CHAPTER 27
INSTRUCTION SET
CHAPTER 28
ELECTRICAL
SPECIFICATIONS
(TARGET)
Chapter
(5/20)
889
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