UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 358

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

356
Figure 12-1 shows the block diagram of serial array unit 0.
Serial data input pin
(when CSI10: SI10/
(when IIC10: SDA10/
(when UART1: R
Serial clock I/O pin
(when CSI10: SCK10/
(when IIC10: SCL10/
Serial data input pin
(when CSI00: SI00/
(when UART0: RxD0/
Serial clock I/O pin
(when CSI01: SCK01/P43)
(when CSI00: SCK00
Serial data input pin
(when CSI01: SI01/P44)
Serial clock I/O pin
When UART0
When UART1
P03/RxD1/SDA10)
P03/RxD1/SI10)
P03/SI10/SDA10)
P04/SCL10)
P04/SCK10)
INTTM02
P11/RxD0)
P11/SI00)
X
/P10)
D1/
Peripheral enable
register 0 (PER0)
f
CLK
SAU0EN
SNFEN00
elimination
Channel 0
Channel 3
enabled/
disabled
Channel 2
SNFEN10
TXE
Channel 1
Noise
elimination
00
enabled/
disabled
Selector
Noise
PM10
RXE
PRS
00
013
detection
Edge
DAP
00
PRS
Edge/level
012
detection
Serial clock select register 0 (SPS0)
Edge/level
Edge/level
Edge/level
detection
Serial communication operation setting register 00 (SCR00)
detection
detection
0
CK01
4
CK01
CK01
CK01
Output latch
Selector
CKP
Figure 12-1. Block Diagram of Serial Array Unit 0
PRS
(P10)
00
011
SCK
0
f
CLK
EOC
CK00
00
PRS
010
/2
Prescaler
CK00
0
CK00
0
CK00
to f
CKS00
PTC
001
CHAPTER 12 SERIAL ARRAY UNIT
CLK
PRS
003
Serial mode register 00 (SMR00)
/2
MCK
0
11
CCS00 STS00 MD002
Selector
PTC
000
PRS
002
(Clock division setting block)
User’s Manual U17893EJ8V0UD
1
4
f
f
CLK
CLK
DIR
00
PRS
CKO02 CKO01 CKO00
001
/2
/2
0
11
to
Serial output register 0 (SO0)
SLC
001
PRS
000
Serial data register 00 (SDR00)
MD001
SLC
000
TCLK
DLS
002
(Buffer register block)
0
DLS
001
Shift register
Communication controller
Communication controller
Communication controller
0
Communication controller
(for transmission)
CSI00 or UART0
DLS
(for transmission)
Mode selection
000
Mode selection
Mode selection
CSI01 or UART0
CSI10 or IIC10
(for reception)
Mode selection
(for reception)
or UART1
0
UART1
0
TSF
00
Serial status register 00 (SSR00)
ST03
SE03 SE02 SE01
SS03 SS02 SS01
0
BFF
1
0
00
SOL02
SOE02 SOE01 SOE00
SO02 SO01
ST02 ST01
Serial flag clear trigger
register 00 (SIR00)
FECT
Output latch
FEF
00
00
(P12)
Error controller
Error controller
Error controller
controller
PECT
controller
0
Interrupt
PEF
Output
00
00
SOL00
SO00
ST00
SE00
SS00
OVCT
OVF
00
00
information
Clear
PM12
Error
Serial channel enable
status register 0 (SE0)
Serial channel start
register 0 (SS0)
Serial channel stop
register 0 (ST0)
Serial output enable
register 0 (SOE0)
Serial output level
register 0 (SOL0)
SNFEN
Noise filter enable
register 0 (NFEN0)
10
Serial data output pin
(when CSI00: SO00/
(when UART0: TXD0/
Serial transfer end interrupt
(when CSI10: INTCSI10)
(when IIC10: INTIIC10)
(when UART1: INTST1)
Serial transfer error interrupt
(INTSRE1)
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when UART0: INTST0)
Serial transfer end interrupt
(when UART1: INTSR1)
Serial transfer error interrupt
(INTSRE0)
Serial data output pin
(when CSI10: SO10/
(when IIC10: SDA10
(when UART1: TXD1/
Serial data output pin
(when CSI01: SO01/P45)
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when UART0: INTSR0)
SNFEN
00
P12/TxD0)
P12/SO00)
P02/TxD1)
P03/SI10/RxD1)
P02/SO10)