UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 866

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

864
3-wire serial I/O
(CSI00, CSI01,
CSI10, CSI20)
communication
UART (UART0,
UART1,
UART2,
UART3)
communication
Simplified
I
IIC20)
communi-
cation
Serial
interface
IIC0
2
Function
C (IIC10,
Slave
transmission/
reception (in
continuous
transmission/
reception mode)
UART
transmission
UART
transmission (in
continuous
transmission
mode)
UART reception
Calculating baud
rate
Address field
transmission
Data reception
Calculating
transfer rate
IIC0: IIC shift
register 0
PER0:
Peripheral
enable register 0
IICC0: IIC
control register 0
IICF0: IIC flag
register 0
Details of
Function
−
The MDmn0 bit can be rewritten even during operation.
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
before the transfer end interrupt of the last transmit data.
When using serial array units 0 and 1 as UARTs, the channels of both the
transmitting side (even-number channel) and the receiving side (odd-number
channel) can be used only as UARTs.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
However, rewrite it before transfer of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last transmit data.
For the UART reception, be sure to set SMRmr of channel r that is to be paired with
channel n.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
Setting SDRmn [15:9] = (0000000B, 0000001B) is prohibited.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
completed by setting “1” to the STmn bit to stop operation and generating a stop
condition.
Setting SDRmn[15:9] = 0000000B is prohibited. Setting SDRmn[15:9] = 0000001B or
more.
Do not write data to IIC0 during data transfer.
Write or read IIC0 only during the wait period. Accessing IIC0 in a communication
state other than during the wait period is prohibited. When the device serves as the
master, however, IIC0 can be written only once after the communication trigger bit
(STT0) is set to 1.
When setting serial interface IIC0, be sure to set IIC0EN to 1 first. If IIC0EN = 0,
writing to a control register of serial interface IIC0 is ignored, and, even if the register
is read, only the default value is read (except for port mode register 6 (PM6) and port
register 6 (P6)).
Be sure to clear bit 1 of the PER0 register to 0.
The start condition is detected immediately after I
while the SCL0 line is at high level and the SDA0 line is at low level. Immediately
after enabling I
manipulation instruction.
When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1
during the ninth clock and wait is canceled, after which TRC0 is cleared and the
SDA0 line is set to high impedance.
Write to STCEN only when the operation is stopped (IICE0 = 0).
ACK is not output when the last data is received (NACK). Communication is then
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
2
C to operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory
Cautions
2
C is enabled to operate (IICE0 = 1)
p.433
p.438
pp.442,
446, 448
p.447
pp.450,
451
pp.452,
455
p.464
p.472
p.481
p.483
p.497
p.500
p.500
p.501
p.504
p.508
p.497
(19/34)
Page