UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 896

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

894
4th edition
Edition
Change of description in 6.3 (14) Noise filter enable register 1 (NFEN1)
Change of 6.5.1 TI0n edge detection circuit
Change of Figure 7-1 Block Diagram of Real-Time Counter
Addition of Caution 3 to Table 8-4 Setting Window Open Period of Watchdog
Timer
Fixing of the SOEm3 and SOE11 bit settings to “0”.
Fixing of the SOm3, SO11, CKOm3, CKO11, and CKO12 bit settings to “1”.
Change of “Setting disabled (set to the initial value)” in Remark
Change of Figure 12-1 Block Diagram of Serial Array Unit 0
Change of Figure 12-2 Block Diagram of Serial Array Unit 1
Addition of settings and Note to Figure 12-5 Format of Serial Clock Select
Register m (SPSm)
Change of Figure 12-14 Format of Serial Output Enable Register m (SOEm)
Addition of description to 12.3 (12) Serial output register m (SOm)
Change of Figure 12-15 Format of Serial Output Register m (SOm)
Addition of Note to transfer rate
Change of transfer rate and Note in 12.4.4 Slave transmission
Change of transfer rate in 12.4.5 Slave reception
Change of transfer rate in 12.4.6 Slave transmission/reception
Change of Note in 12.4.7 (2)
Addition of setting and Note to Table 12-2 Operating Clock Selection
Change of transfer rate and addition of Note
Change of Figure 12-74 Example of Contents of Registers for UART Reception
of UART (UART0, UART1, UART2, UART3)
Change of Figure 12-77 Procedure for Resuming UART Reception
Addition of setting and Note to Table 12-3 Operating Clock Selection
Change of Figure 12-92 Flowchart of Data Transmission
Addition of setting and Note to Table 12-4 Operating Clock Selection
Change of Figure 15-9 Example of Setting for UART Consecutive Reception + ACK
Transmission
Additions of description to 15.6 (4) DMA pending instruction
Change of Figure 18-4 HALT Mode Release by Reset
Change of Figure 18-7 STOP Mode Release by Reset
Change of reset processing in Figure 19-2 Timing of Reset by RESET Input
Change of reset processing in Figure 19-4 Timing of Reset in STOP Mode by
RESET Input
Change of Caution 2 in Figure 19-5 Format of Reset Control Flag Register
(RESF)
Change of Figure 20-2 Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector (1/2)
Change of Figure 20-2 Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector (2/2) and addition of Note
Change of Figure 20-3 Example of Software Processing After Reset Release
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
Description
CHAPTER 6 TIMER
ARRAY UNIT
CHAPTER 7 REAL-
TIME COUNTER
CHAPTER 8
WATCHDOG TIMER
CHAPTER 12 SERIAL
ARRAY UNIT
CHAPTER 15 DMA
CONTROLLER
CHAPTER 18
STANDBY FUNCTION
CHAPTER 19 RESET
FUNCTION
CHAPTER 20 POWER-
ON-CLEAR CIRCUIT
Chapter
(10/20)