UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 455

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
(Selective)
(Essential)
(Essential)
Changing setting of SPSm register
Changing setting of SDRmn register
Changing setting of SCRmn register
Manipulating target for communication
Changing setting of SMRmn
Starting setting for resumption
Starting communication
Figure 12-82. Procedure for Resuming UART Reception
Writing to SSm
and SMRmr registers
Clearing error flag
CHAPTER 12 SERIAL ARRAY UNIT
register
User’s Manual U17893EJ8V0UD
Stop the target for communication or wait
until the target completes its operation.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn and SMRmr registers is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
The start bit is detected.
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