UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 480

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
12.7.3 Data reception
After all data are received to the slave, a stop condition is generated and the bus is released.
Note To perform communication via simplified I
Remark
478
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data level
Parity bit
Stop bit
Data direction
Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field.
Simplified I
POM143 = 1) for the port output mode registers (POM0, POM14) (see 4.3 Registers Controlling Port
Function for details). When communicating with an external device with a different potential, set the N-ch
open-drain output (V
SCL20) (see 4.4.4 Connecting to external device with different potential (2.5 V, 3 V) for details).
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
2
C
Channel 2 of SAU0
SCL10, SDA10
INTIIC10
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Overrun error detection flag (OVFmn) only
8 bits
Max. f
However, the following condition must be satisfied in each mode of I
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Forward output (default: high level)
No parity bit
Appending 1 bit (ACK transmission)
MSB first
DD
MCK
tolerance) mode (POM04, POM142 = 1) also for the clock input/output pins (SCL10,
/4 [Hz] (SDRmn[15:9] = 1 or more)
Note
CHAPTER 12 SERIAL ARRAY UNIT
IIC10
User’s Manual U17893EJ8V0UD
2
C, set the N-ch open-drain output (V
f
MCK
: Operation clock (MCK) frequency of target channel
Channel 0 of SAU1
SCL20, SDA20
INTIIC20
2
C.
Note
DD
IIC20
tolerance) mode (POM03,