UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 607

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
Cautions 1. Be sure to clear bits 1 to 7 of IF2H to 0.
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
MK0L, MK0H, MK1L, MK1H, MK2L, and MK2H can be set by a 1-bit or 8-bit memory manipulation instruction.
When MK0L and MK0H, MK1L and MK1H, and MK2L and MK2H are combined to form 16-bit registers MK0,
MK1, and MK2, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
Address: FFFD1H
Symbol
Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (2/2)
IF2H
increases by 2 clocks.
2. When operating a timer, serial interface, or A/D converter after standby release, operate it
3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler
must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction
such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
In this case, even if the request flag of another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared
to 0 at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory
manipulation instruction in C language.
XXIFX
mov a, IF0L
and a, #0FEH
mov IF0L, a
7
0
0
1
After reset: 00H
No interrupt request signal is generated
Interrupt request is generated, interrupt request status
6
0
CHAPTER 16 INTERRUPT FUNCTIONS
R/W
User’s Manual U17893EJ8V0UD
5
0
4
0
Interrupt request flag
3
0
2
0
1
0
PIF11
<0>
605