UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 893

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3rd edition
Edition
Addition of Table 6-4 Operations from Count Operation Enabled State to TCR0n
Count Start, and (a) through (e)
Addition of description to 6.3 (11) Timer output level register 0 (TOL0)
Change of description of 6.3 (12) Timer output mode register 0 (TOM0)
Change of Figure 6-20 Format of Timer Output Mode Register 0 (TOM0) and
Remark
Change of description of bit 7 and addition of Note in Figure 6-22 Format of Noise
Filter Enable Register 1 (NFEN1)
Addition of 6.4 Channel Output (TO0n pin) Control
Addition of 6.5 Channel Input (TI0n Pin) Control
Addition of MD0n0 bit condition to titles in the following figures
• Figure 6-37 Example of Basic Timing of Operation as Interval Timer/Square
Wave Output
• Figure 6-45 Example of Basic Timing of Operation as Frequency Divider
(MD0n0 = 1)
• Figure 6-49 Example of Block Diagram of Operation as Input Pulse Interval
Measurement
Change of description of 6.7.3 Operation as frequency divider
Change of description of 6.8.3 Operation as multiple PWM output function
Change of clear conditions of real-time counter
Change of description and Caution 1 in Figure 7-2 Format of Peripheral Enable
Register 0 (PER0)
Addition of Caution 2 to Figure 7-2 Format of Peripheral Enable Register 0
(PER0)
Addition of Caution to Figure 7-4 Format of Real-Time Counter Control Register
1 (RTCC1)
Addition of Caution to Figure 7-5 Format of Real-Time Counter Control Register 2
(RTCC2)
Change of Note 2 in 7.3 (5) Sub-count register (RSUBC)
Change of bit name in Figure 7-17 Format of Alarm Week Register (ALARMWW)
Addition of Caution 2 to 10.3 (1) Peripheral enable register 0 (PER0)
Change of Table 10-2 A/D Conversion Time Selection
Addition of Caution 2 to 11.3 (1) Peripheral enable register 0 (PER0)
Addition of Caution 3 to 12.3 (1) Peripheral enable register 0 (PER0)
Changes of Figure 12-7 Format of Serial Communication Operation Setting
Register mn (SCRmn)
Addition of description to 12.3 (13) Serial output level register m (SOLm)
Changes of bits 1 and 3 in Figure 12-16 Format of Serial Output Level Register m
(SOLm)
Changes of setting of (a) Serial output register m (SOm), (d) Serial output level
register m (SOLm), and Note in Figure 12-66 Example of Contents of Registers
for UART Transmission of UART (UART0, UART1, UART2, UART3)
(MD0n0 = 1)
(MD0n0 = 0)
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
Description
CHAPTER 6 TIMER
ARRAY UNIT
CHAPTER 7 REAL-
TIME COUNTER
CHAPTER 10 A/D
CONVERTER
CHAPTER 11 D/A
CONVERTER
CHAPTER 12 SERIAL
ARRAY UNIT
Chapter
(7/20)
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