UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 211

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(a) Start timing in interval timer mode
Caution In the first cycle operation of count clock after writing TS0n, an error at a maximum of one
<1> Writing 1 to TS0n sets TE0n = 1
<2> The write data to TS0n is held until count clock generation.
<3> TCR0n holds the initial value until count clock generation.
<4> On generation of count clock, the “TDR0n value” is loaded to TCR0n and count starts.
Table 6-4. Operations from Count Operation Enabled State to TCR0n Count Start (2/2)
• One-count mode
• Capture & one-count mode
Start trigger detection signal
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start
by setting MD0n0 = 1.
Timer operation mode
TS0n (write) hold signal
TS0n (write)
Count clock
INTTM0n
Figure 6-10. Start Timing (In Interval Timer Mode)
TCR0n
TE0n
f
CLK
CHAPTER 6 TIMER ARRAY UNIT
<1>
When TS0n = 0, writing 1 to TS0n bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of TDR0n to TCR0n and the subsequent
count clock performs count down operation (see 6.3 (6) (d) Start timing in one-
count mode).
When TS0n = 0, writing 1 to TS0n bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCR0n and the subsequent count clock
performs count up operation (see 6.3 (6) (e) Start timing in capture & one-
count mode).
User’s Manual U17893EJ8V0UD
<2>
Initial value
<3>
Operation when TS0n = 1 is set
TDR0n value
When MD0n0 = 1 is set
<4>
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