UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 370

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
368
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01),
(5) Higher 7 bits of the serial data register mn (SDRmn)
SDRmn
Symbol
Cautions 1. Be sure to clear bit 8 to “0”.
For the function of the lower 8 bits of SDRmn, see 12.2 Configuration of Serial Array Unit.
SDRmn can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During
operation (SEmn = 1), a value is written only to the lower 8 bits of SDRmn. When SDRmn is read during
operation, 0 is always read.
Reset signal generation clears this register to 0000H.
Remarks 1. For the function of the lower 8 bits of SDRmn, see 12.2 Configuration of Serial Array Unit.
SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 7 to 0 function as a transmit/receive
buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (MCK).
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating
clock by the higher 7 bits of SDRmn is used as the transfer clock.
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03),
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11),
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13)
15
0
0
0
0
1
1
•
•
•
2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I
4. Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If these
2. m: Unit number (m = 0, 1)
SDRmn[15:9] to 0000001B or greater.
bits are written to, the higher seven bits are cleared to 0.)
n: Channel number (n = 0 to 3)
14
0
0
0
0
1
1
•
•
•
13
Figure 12-8. Format of Serial Data Register mn (SDRmn)
0
0
0
0
1
1
•
•
•
SDRmn[15:9]
FFF11H (SDR00)
12
0
0
0
0
1
1
•
•
•
CHAPTER 12 SERIAL ARRAY UNIT
11
0
0
0
0
1
1
•
•
•
User’s Manual U17893EJ8V0UD
10
0
0
1
1
1
1
•
•
•
9
0
1
0
1
0
1
•
•
•
8
0
Transfer clock setting by dividing the operating clock (MCK)
After reset: 0000H
7
6
5
R/W
FFF10H (SDR00)
MCK/254
MCK/256
MCK/2
MCK/4
MCK/6
MCK/8
4
•
•
•
3
2
C is used. Set
2
1
0