UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 890

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

888
2nd edition
Edition
Modification of Caution and addition of Remark in Figure 8-2 Format of Peripheral
Enable Register 0 (PER0)
Modification of Caution in 8.3 (2) Real-time counter control register 0 (RTCC0)
Modification of Caution in 8.3 (3) Real-time counter control register 1 (RTCC1)
Addition of Remark in Figure 8-4 Format of Real-Time Counter Control Register
1 (RTCC1) and Figure 8-21 Alarm Setting Procedure
Change of reset value and addition of description in 8.3 (8) Hour count register
(HOUR)
Change of reset value of 8.3 (9) Day count register (DAY)
Change of reset value of 8.3 (11) Month count register (MONTH)
Change of reset value of 8.3 (15) Alarm hour register (ALARMWH)
Addition of Caution to 11.3 (7) Port mode registers 2 and 15 (PM2, PM15)
Addition of Caution on PER0 and SPSm registers in 13.4 Operation of 3-Wire
Serial I/O (CSI00, CSI01, CSI10, CSI20) Communication through 13.6 Operation
of Simplified I2C (IIC10, IIC20) Communication
Addition of SFR name for the lower 8 bits of registers SSRmn, SIRmn, Semn, SSm,
STm, SPSm, some and SOLm in 13.3 Registers Controlling Serial Array Unit
Change of R/W attribute of registers SIRmn, SSm, and STm in 13.3 Registers
Controlling Serial Array Unit.
Change of reset value of 13.3 (12) Serial output register m (Som).
Modification of bit 0 setting in Figure 13-36 (d) Serial mode register mn (SMRmn).
Deletion of description on overrun error in 13.6 Operation of Simplified I2C (IIC10,
IIC20) Communication.
Deletion of description on overrun error in 13.6.1 Address field transmission.
Deletion of description on overrun error in 13.6.2 Data transmission.
Deletion of description on overrun error in 13.6.3 Data reception.
Addition of 14.5.18 Timing of I2C interrupt request (INTIIC0) occurrence.
Addition of 14.6 Timing Charts.
Change of symbols of higher multiplication result storage register and lower
multiplication result storage register in CHAPTER 15.
Addition of Figure 15-2 Format of 16-bit higher multiplication result storage
register and 16-bit lower multiplication result storage register (MULOH,
MULOL).
Addition of Figure 15-3 Format of Multiplication input data registers A, B (MULA,
MULB).
Addition of Note in 16.2 (1) DMA SFR address register n (DSAn).
Addition of Note in Table 17-2 Flags Corresponding to Interrupt Request
Sources.
Change of bit name of bits 0 to 2 of the IF2L register in Figure 17-2.
Chang of bit name of bits 0 of the MK0L register in Figure 17-3.
Modification of 17.4.4 Interrupt request hold.
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
Description
CHAPTER 8 REAL-
TIME COUNTER
CHAPTER 11 A/D
CONVERTER
CHAPTER 13 SERIAL
ARRAY UNIT
CHAPTER 14 SERIAL
INTERFACE IIC0
CHAPTER 15
MULTIPLIER
CHAPTER 16 DMA
CONTROLLER
CHAPTER 17
INTERRUPT
FUNCTIONS
Chapter
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