UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 359

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial data input pin
(when CSI20: SI20/
(when IIC20: SDA20/
(when UART2: RxD2/
Serial clock I/O pin
(when CSI20: SCK20/
(when IIC20: SCL20/
Figure 12-2 shows the block diagram of serial array unit 1.
Serial data input pin
(when UART3: RxD3/P14)
When UART2
When UART3
P143/RxD2/SDA20)
P143/RxD2/SI20)
P143/SI20/SDA20)
P142/SCL20)
P142/SCK20)
INTTM03
Peripheral enable
register 0 (PER0)
f
CLK
SAU1EN
SNFEN20
Channel 2 (LIN-bus supported)
Channel 3 (LIN-bus supported)
elimination
Channel 0
SNFEN30
enabled/
disabled
TXE
Channel 1
elimination
Noise
10
enabled/
disabled
Noise
PM142
RXE
PRS
10
113
detection
Edge
DAP
Edge/level
Edge/level
10
Edge/level
PRS
detection
112
detection
detection
Serial clock select register 1 (SPS1)
Serial communication operation setting register 10 (SCR10)
CK11
4
0
Output latch
CK11
Figure 12-2. Block Diagram of Serial Array Unit 1
Selector
CK11
CK11
CKP
(P142)
PRS
10
111
SCK
0
f
CLK
EOC
10
PRS
/2
CK10
110
Prescaler
0
to f
0
CK10
CK10
CK10
CHAPTER 12 SERIAL ARRAY UNIT
CLK
CKS10
PTC
101
PRS
103
/2
Serial mode register 10 (SMR10)
MCK
11
0
CCS10 STS10 MD102
Selector
PTC
100
PRS
User’s Manual U17893EJ8V0UD
102
(Clock division setting block)
4
1
f
f
CLK
CLK
DIR
PRS
10
101
/2
/2
0
11
1
to
SLC
101
PRS
100
Serial data register 10 (SDR10)
Serial output register 1 (SO1)
1
MD101
SLC
100
TCLK
CKO10
DLS
102
(Buffer register block)
0
DLS
101
Shift register
Communication controller
Communication controller
Communication controller
Communication controller
0
(for transmission)
DLS
(for transmission)
100
Mode selection
Mode selection
Mode selection
CSI20 or IIC20
Mode selection
(for reception)
(for reception)
or UART2
0
UART3
UART3
UART2
TSF
0
10
Serial status register 10 (SSR10)
SE13 SE12 SE11
SS13 SS12 SS11
ST13
BFF
1
0
10
0
Serial flag clear trigger
register 10 (SIR10)
SOE12
SOL12
(P144 or p143)
SO12
ST12 ST11
Output latch
FECT
FEF
10
10
Error controller
Error controller
Error controller
controller
PECT
controller
PEF
Interrupt
1
0
0
Output
10
10
SOL10
SOE10
SO10
PM144 or PM143
SE10
SS10
ST10
OVCT
OVF
10
10
information
Clear
Error
Serial channel enable
status register 1 (SE1)
Serial channel start
register 1 (SS1)
Serial channel stop
register 1 (ST1)
Serial output enable
register 1 (SOE1)
Serial output level
register 1 (SOL1)
Noise filter enable
register 0 (NFEN0)
SNFEN
30
Serial transfer end interrupt
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
Serial transfer end interrupt
(when UART2: INTSR2)
Serial transfer end interrupt
(when UART3: INTSR3)
Serial data output pin
(when CSI20: SO20/
(when IIC20: SDA20/
(when UART2: TxD2/
Serial transfer error interrupt
(INTSRE2)
Serial transfer end interrupt
(when UART3: INTST3)
Serial transfer error interrupt
(INTSRE3)
SNFEN
Serial data output pin
(when UART3: T
20
P144/TxD2)
P143/SI20/RxD2)
P144/SO20)
X
D3/P13)
357