UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 322

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) 10-bit A/D conversion result register (ADCR)
(4) 8-bit A/D conversion result register (ADCRH)
320
Symbol
ADCR
Caution When writing to the A/D converter mode register (ADM), analog input channel specification
Caution When writing to the A/D converter mode register (ADM), analog input channel specification
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8
bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of FFF1EH.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are
stored.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FFF1FH, FFF1EH
register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may become
undefined. Read the conversion result following conversion completion before writing to ADM,
ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to
be read.
register (ADS), and A/D port configuration register (ADPC), the contents of ADCRH may become
undefined. Read the conversion result following conversion completion before writing to ADM,
ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to
be read.
Address: FFF1FH
ADCRH
Symbol
Figure 10-8. Format of 8-Bit A/D Conversion Result Register (ADCRH)
Figure 10-7. Format of 10-Bit A/D Conversion Result Register (ADCR)
7
FFF1FH
After reset: 00H
After reset: 0000H
6
CHAPTER 10 A/D CONVERTER
User’s Manual U17893EJ8V0UD
5
R
4
R
3
2
0
FFF1EH
0
1
0
0
0
0
0