UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 668

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

666
(b) When LVI default start function enabled is set (option byte: LVIOFF = 0)
Cautions 1. Even when the LVI default start function is used, if it is set to LVI operation prohibition by
• When starting operation
• When stopping operation
Figure 21-9 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <3> above.
Either of the following procedures must be executed.
•
•
<1>
<2> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
<3>
<4>
Write 00H to LVIM.
Clear LVION to 0.
When using 8-bit memory manipulation instruction:
When using 1-bit memory manipulation instruction:
2. When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the LVIRF flag
Start in the following initial setting state.
Release the interrupt mask flag of LVI (LVIMK).
Execute the EI instruction (when vector interrupts are used).
•
•
•
•
•
For details of RESF, see CHAPTER 19 RESET FUNCTION.
the software, it operates as follows:
may become 1 from the beginning due to the power-on waveform.
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation)
Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected)
Set the low-voltage detection level selection register (LVIS) to 0EH (default value: V
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply
Set bit 0 (LVIF) of LVIM to 0 (Detects falling edge “Supply voltage (V
voltage (V
±0.1 V).
(V
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts
LVI
after reset release. There is a period when low-voltage detection cannot be performed
normally, however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting
for the LVI stabilization time.
)”)
DD
))
CHAPTER 21 LOW-VOLTAGE DETECTOR
User’s Manual U17893EJ8V0UD
DD
) ≥ detection voltage
LVI
μ
= 2.07 V
s max.,