UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 413

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UPD78F1152AGC-GAD-AX

Manufacturer Part Number
UPD78F1152AGC-GAD-AX
Description
MCU 16BIT 78K0R/KX3 80-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1152AGC-GAD-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1152AGC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.5.4 Slave transmission
input from another device.
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
Slave transmission is that the 78K0R/KF3 transmits data to another device in the state of a transfer clock being
Notes 1. Because the external serial clock input to pins SCK00, SCK01, SCK10, and SCK20 is sampled internally
Remarks 1. f
3-Wire Serial I/O
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
and used, the fastest transfer rate is f
electrical specifications (see CHAPTER 28
PRODUCTS) and CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
MCK
: Operation clock (MCK) frequency of target channel
Channel 0 of SAU0
SCK00, SO00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Overrun error detection flag (OVFmn) only
7 or 8 bits
Max. f
Selectable by DAPmn bit
• DAPmn = 0: Data output starts from the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
MSB or LSB first
MCK
CSI00
/6 [Hz]
Notes 1, 2
CHAPTER 12 SERIAL ARRAY UNIT
User’s Manual U17893EJ8V0UD
Channel 1 of SAU0
SCK01, SO01
INTCSI01
MCK
/6 [Hz].
CSI01
ELECTRICAL SPECIFICATIONS (STANDARD
SCK10, SO10
INTCSI10
Channel 2 of SAU0
CSI10
Channel 0 of SAU1
SCK20, SO20
INTCSI20
CSI20
411

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