UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 864

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

862
D/A
converter
Configuration
of serial
array unit
Registers
controlling
serial array
unit
Function
Reducing power
consumption in
STOP mode
Output
impedance of
D/A converter
SDRmn: Lower
8 bits of the
serial data
register mn
PER0:
Peripheral
enable register 0
SPSm: Serial
clock select
register m
SMRmn: Serial
mode register
mn
SCRmn: Serial
communication
operation setting
register mn
SDRmn: Higher
7 bits of the
serial data
register mn
SIRmn: Serial
flag clear trigger
register mn
SSm: Serial
channel start
register m
STm: Serial
channel stop
register m
Details of
Function
Because the D/A converter stops operation in the STOP mode, the ANO0 and ANO1
pins go into a high impedance state, and the power consumption can be reduced. In
the standby modes other than the STOP mode, however, the operation continues.
To lower the power consumption, therefore, clear the DACEn bit of the DAM register
to 0 (D/A conversion stop).
Since the output impedance of the D/A converter is high, the current cannot be
obtained from the ANOn pin (n = 0, 1). When the input impedance of the load is low,
insert a follower amplifier between the load and ANOn pin keeping the wiring length
as short as possible (for high impedance). If the wiring becomes too long, take
necessary actions such as surrounding with a ground pattern.
Be sure to clear bit 8 to “0”.
When setting serial array unit m, be sure to set SAUmEN to 1 first. If SAUmEN = 0,
writing to a control register of serial array unit m is ignored, and, even if the register is
read, only the default value is read (except for input switch control register (ISC),
noise filter enable register (NFEN0), port input mode registers (PIM0, PIM4, PIM14),
port output mode registers (POM0, POM4, POM14), port mode registers (PM0, PM1,
PM4, PM14), and port registers (P0, P1, P4, P14)).
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
Be sure to clear bit 1 of the PER0 register to 0.
Be sure to clear bits 15 to 8 to “0”.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Be sure to clear bit 8 to “0”.
Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
Setting SDRmn[15:9] = 0000000B is prohibited when simplified I
SDRmn[15:9] to 0000001B or greater.
Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If
these bits are written to, the higher seven bits are cleared to 0.)
Be sure to clear bits 15 to 3 to “0”.
Be sure to clear bits 15 to 4 to “0”.
Be sure to clear bits 15 to 4 to “0”.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
Cautions
2
C is used. Set
p.359
p.361
p.361
p.361
p.362
p.362
p.363
pp.365
to 367
p.368
p.368
p.368
p.368
p.371
p.373
p.374
p.351
p.351
(17/34)
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