UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 856

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

854
Timer
array unit
Function
Channel output
(TO0n pin)
operation
TOL0: Timer
output level
register 0
TOM0: Timer
output mode
register 0
ISC: Input switch
control register
Collective
manipulation of
TO0n bits
Details of
Function
When TOE0n = 1, even if the output by timer interrupt of each timer (INTTM0n)
contends with writing to TO0n, output is normally done to TO0n pin.
Be sure to clear bits 15 to 8 to “0”.
Be sure to clear bits 15 to 8 to “0”.
Be sure to clear bits 7 to 2 to “0”.
(1) Changing values set in registers TO0, TOE0, TOL0, and TOM0 during timer
operation
Since the timer operations (operations of TCR0n and TDR0n) are independent of the
TO0n output circuit and changing the values set in TO0, TOE0, TOL0, and TOM0
does not affect the timer operation, the values can be changed during timer
operation. To output an expected waveform from the TO0n pin by timer operation,
however, set TO0, TOE0, TOL0, and TOM0 to the values stated in the register
setting example of each operation.
When the values set in TOE0, TOL0, and TOM0 (except for TO0) are changed close
to the timer interrupt (INTTM0n), the waveform output to the TO0n pin may be
different depending on whether the values are changed immediately before or
immediately after the timer interrupt (INTTM0n) signal generation timing.
(2) Default level of TO0n pin and output level after timer operation start
The following figure shows the TO0n pin output level transition when writing has been
done in the state of TOE0n = 0 before port output is enabled and TOE0n = 1 is set
after changing the default level.
(a) When operation starts with TOM0n = 0 setting (toggle output)
(b) When operation starts with TOM0n = 1 setting (combination operation mode
(3) Operation of TO0n pin in combination operation mode (TOM0n = 1)
(a) When TOL0n setting has been changed during timer operation
(b) Set/reset timing
The setting of TOL0n is invalid when TOM0n = 0. When the timer operation
starts after setting the default level, the toggle signal is generated and the output
level of TO0n pin is reversed.
(PWM output))
When TOM0n = 1, the active level is determined by TOL0n setting.
When the TOL0n setting has been changed during timer operation, the setting
becomes valid at the generation timing of TO0n change condition. Rewriting
TOL0n does not change the output level of TO0n. The following figure shows the
operation when the value of TOL0n has been changed during timer operation
(TOM0n = 1).
To realize 0%/100% output at PWM output, the TO0n pin/TO0n set timing at
master channel timer interrupt (INTTM0n) generation is delayed by 1 count clock
by the slave channel.
If the set condition and reset condition are generated at the same time, a higher
priority is given to the latter.
Figure 6-29 shows the set/reset operating statuses where the master/slave
channels are set as follows.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
Cautions
p.216
p.217
p.218
p.222
pp.223,
224
pp.224,
225
p.227
Page
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