UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 15

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 13 SERIAL INTERFACE IIC0 ........................................................................................... 494
CHAPTER 14 MULTIPLIER .................................................................................................................. 567
CHAPTER 15 DMA CONTROLLER..................................................................................................... 570
12.8 Relationship Between Register Settings and Pins ............................................................... 487
13.1 Functions of Serial Interface IIC0 ........................................................................................... 494
13.2 Configuration of Serial Interface IIC0..................................................................................... 497
13.3 Registers to Controlling Serial Interface IIC0........................................................................ 500
13.4 I
13.5 I
13.6 Timing Charts ........................................................................................................................... 560
14.1 Functions of Multiplier............................................................................................................. 567
14.2 Configuration of Multiplier ...................................................................................................... 568
14.3 Operation of Multiplier............................................................................................................. 569
15.1 Functions of DMA Controller .................................................................................................. 570
15.2 Configuration of DMA Controller............................................................................................ 571
15.3 Registers Controlling DMA Controller ................................................................................... 574
15.4 Operation of DMA Controller .................................................................................................. 578
15.5 Example of Setting of DMA Controller................................................................................... 581
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13.4.1 Pin configuration ...........................................................................................................................512
13.5.1 Start conditions .............................................................................................................................513
13.5.2 Addresses .....................................................................................................................................514
13.5.3 Transfer direction specification .....................................................................................................514
13.5.4 Transfer clock setting method .......................................................................................................515
13.5.5 Acknowledge (ACK) ......................................................................................................................516
13.5.6 Stop condition ...............................................................................................................................518
13.5.7 Wait...............................................................................................................................................519
13.5.8 Canceling wait...............................................................................................................................521
13.5.9 Interrupt request (INTIIC0) generation timing and wait control......................................................522
13.5.10 Address match detection method................................................................................................523
13.5.11 Error detection ............................................................................................................................523
13.5.12 Extension code ...........................................................................................................................523
13.5.13 Arbitration....................................................................................................................................524
13.5.14 Wakeup function .........................................................................................................................525
13.5.15 Communication reservation ........................................................................................................526
13.5.16 Cautions......................................................................................................................................530
13.5.17 Communication operations .........................................................................................................531
13.5.18 Timing of I
15.4.1 Operation procedure .....................................................................................................................578
15.4.2 Transfer mode...............................................................................................................................580
15.4.3 Termination of DMA transfer .........................................................................................................580
15.5.1 CSI consecutive transmission .......................................................................................................581
15.5.2 CSI master reception ....................................................................................................................583
15.5.3 CSI transmission/reception ...........................................................................................................585
15.5.4 Consecutive capturing of A/D conversion results..........................................................................587
C Bus Mode Functions .......................................................................................................... 512
C Bus Definitions and Control Methods .............................................................................. 513
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C interrupt request (INTIIC0) occurrence ..................................................................539
User’s Manual U17893EJ8V0UD
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