UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 868

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

866
Serial
interface
IIC0
DMA
controller
Function
STT0, SPT0:
Bits 1, 0 of IIC
control register 0
(IICC0)
DBCn: DMA
byte count
register n
DRCn: DMA
operation control
register n
Holding DMA
transfer pending
by DWAITn
Forced
Termination of
DMA Transfer
Priority
Response time
Operation in
standby mode
DMA pending
instruction
Details of
Function
When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt
request is generated when the stop condition is detected. Transfer is started when
communication data is written to IIC0 after the interrupt request is generated. Unless
the interrupt is generated when the stop condition is detected, the device stops in the
wait state because the interrupt request is not generated when communication is
started. However, it is not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0)
is detected by software.
Be sure to clear bits 15 to 10 to “0”.
If the general-purpose register is specified or the internal RAM space is exceeded as
a result of continuous transfer, the general-purpose register or SFR space are written
or read, resulting in loss of data in these spaces. Be sure to set the number of times
of transfer that is within the internal RAM space.
The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is
terminated without waiting for generation of the interrupt (INTDMAn) of DMAn,
therefore, set DSTn to 0 and then DENn to 0 (for details, refer to 15.5.7 Forcible
termination by software).
When DMA transfer is held pending while using both DMA channels, be sure to hold
the DMA transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1).
If the DMA transfer of one channel is executed while that of the other channel is held
pending, DMA transfer might not be held pending for the latter channel.
In example 3, the system is not required to wait two clock cycles after DWAITn is set
to 1. In addition, the system does not have to wait two clock cycles after clearing
DSTn to 0, because more than two clock cycles elapse from when DSTn is cleared to
0 to when DENn is cleared to 0.
During DMA transfer, a request from the other DMA channel is held pending even if
generated. The pending DMA transfer is started after the ongoing DMA transfer is
completed. If two DMA requests are generated at the same time, however, DMA
channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA
transfer takes precedence, and then interrupt servicing is executed.
The response time of DMA transfer is as follows. (See Table 15-2.)
The DMA controller operates as follows in the standby mode. (See Table 15-3.)
Even if a DMA request is generated, DMA transfer is held pending immediately after
the following instructions.
• CALL !addr16
• CALL $!addr20
• CALL !!addr20
• CALL rp
• CALLT [addr5]
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L,
MK0H, MK1L, MK1H, MK2L, MK2H, PR00L, PR00H, PR01L, PR01H, PR02L,
PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H and PSW each,
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
Cautions
p.530
p.573
p.573
p.577
p.591
p.593
p.594
p.595
p.595
p.596
(21/34)
Page