UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 50

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.1 Memory Space
48
Products in the 78K0R/KF3 can access a 1 MB memory space. Figures 3-1 to 3-5 show the memory maps.
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
Data memory
space
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7
Program
memory
space
When boot swap is used:
Setting).
F F F F F H
F F F 0 0 H
F E F 0 0 H
F E E F F H
F 1 0 0 0 H
F 0 F F F H
F 0 8 0 0 H
F 0 7 F F H
F 0 0 0 0 H
E F F F F H
1 0 0 0 0 H
0 F F F F H
F F E F F H
F F E E 0 H
F F E D F H
0 0 0 0 0 H
Special function register (2nd SFR)
General-purpose register
Special function register (SFR)
Figure 3-1. Memory Map (
32 bytes
Flash memory
RAM
CHAPTER 3 CPU ARCHITECTURE
55.75 KB
256 bytes
Reserved
Reserved
Mirror
4 KB
2 KB
64 KB
Note 1
security IDs to 000C4H to 000CDH.
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
User’s Manual U17893EJ8V0UD
μ
PD78F1152, 78F1152A)
0 0 0 C E H
0 1 0 C D H
0 1 0 C 4 H
0 1 0 C 3 H
0 1 0 B F H
0 1 0 0 0 H
0 0 F F F H
0 0 0 C D H
0 0 0 C 4 H
0 0 0 C 3 H
0 0 0 C 0 H
0 0 0 B F H
0 0 0 8 0 H
0 0 0 7 F H
0 0 0 0 0 H
0 F F F F H
0 1 0 C E H
0 1 0 C 0 H
0 1 0 8 0 H
0 1 0 7 F H
On-chip debug security
On-chip debug security
Option byte area
Option byte area
ID setting area
ID setting area
CALLT table area
Vector table area
CALLT table area
Vector table area
Program area
Program area
128 bytes
128 bytes
64 bytes
64 bytes
10 bytes
10 bytes
4 bytes
4 bytes
Note 2
Note 2
Note 2
Note 2
0 1 F F F H
Boot cluster 0
Boot cluster 1
Note 3
Security