UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 461

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6.4 LIN reception
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
Remark
Support of LIN communication
Target channel
Pins used
Interrupt
Error interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
Of UART reception, UART3 supports LIN communication.
For LIN reception, channel 3 of unit 1 (SAU1) is used.
Figure 12-87 outlines a reception operation of LIN.
specifications (see CHAPTER 28
CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
f
f
MCK
CLK
UART
: System clock frequency
: Operation clock (MCK) frequency of target channel
Not supported
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
• Framing error detection flag (FEF13)
• Parity error detection flag (PEF13)
• Overrun error detection flag (OVF13)
8 bits
Max. f
Reverse output (default: low level)
• No parity bit (no parity check)
• Appending 0 parity bit (no parity check)
• Appending even parity check
• Appending odd parity check
The following selectable
• Appending 1 bit
• Appending 2 bits
Forward output (default: high level)
The following selectable
MSB or LSB first
MCK
UART0
/6 [bps] (SDR13 [15:9] = 2 or more), Min. f
−
−
−
−
CHAPTER 12 SERIAL ARRAY UNIT
User’s Manual U17893EJ8V0UD
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
Not supported
UART1
−
−
−
−
Not supported
CLK
/(2 × 2
UART2
−
−
−
−
11
× 128) [bps]
Supported
Channel 3 of SAU1
RxD3
INTSR3
INTSRE3
Note
UART3
459