UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 438

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

436
Remarks 1. X: Don’t care
Notes 1. When changing the clock selected for f
2. SAU can be operated at a fixed division ratio of the subsystem clock, regardless of the f
Register
SMRmn
CKSmn
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
value), do so after having stopped (STm = 000FH) the operation of the serial array unit (SAU).
When selecting INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU)
(TT0 = 00FFH).
0
1
frequency (main system clock, subsystem clock), by operating the interval timer for which f
has been selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0
register to 1) and selecting INTTM02 and INTTM03 by using the SPSm register in channels 2 and
3 of TAU. When changing f
above.
PRS
m13
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
PRS
m12
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
Other than above
Table 12-2. Selection of operation clock
PRS
m11
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
1
CHAPTER 12 SERIAL ARRAY UNIT
SPSm Register
PRS
m10
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
1
User’s Manual U17893EJ8V0UD
CLK
PRS
m03
, however, SAU and TAU must be stopped as described in Note 1
0
0
0
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
PRS
m02
0
0
0
0
1
1
1
1
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
CLK
PRS
m01
(by changing the system clock control register (CKC)
0
0
1
1
0
0
1
1
0
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
PRS
m00
X
0
1
0
1
0
1
0
1
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
f
f
f
f
f
f
f
f
f
f
f
f
INTTM02 if m = 0,
INTTM03 if m = 1
f
f
f
f
f
f
f
f
f
f
f
f
INTTM02 if m = 0,
INTTM03 if m = 1
Setting prohibited
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Operation Clock (MCK)
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
8
9
10
11
2
3
4
5
6
7
8
9
10
11
f
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
CLK
Note2
Note2
= 20 MHz
Note1
SUB
CLK
/4