UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 512

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

510
IICX0
CLX0
Bit 0
(6) IIC function expansion register 0 (IICX0)
Caution Determine the transfer clock frequency of I
Remarks 1. ×:
0
0
0
0
0
0
0
1
1
1
1
This register sets the function expansion of I
IICX0 can be set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with
bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock select register 0 (IICCL0) (see 13.5.4 Transfer clock
setting method).
Set IICX0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation clears this register to 00H.
Address: FFF55H
SMC0
Symbol
Bit 3
IICX0
0
0
0
0
1
1
1
0
1
1
1
2. f
enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change
the transfer clock frequency, clear IICE0 once to 0.
CLK
IICCL0
CL01
Bit 1
: CPU/peripheral hardware clock frequency
0
0
1
1
0
1
1
×
0
1
1
don’t care
Figure 13-10. Format of IIC Function Expansion Register 0 (IICX0)
7
0
CL00
Bit 0
After reset: 00H
0
1
0
1
×
0
1
×
×
0
1
6
0
f
f
f
f
f
f
f
Setting prohibited
f
Setting prohibited
f
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Transfer Clock (f
CHAPTER 13 SERIAL INTERFACE IIC0
Table 13-2. Selection Clock Setting
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User’s Manual U17893EJ8V0UD
5
0
R/W
2
C.
CLK
/m)
4
0
4.00 MHz to 8.4 MHz
8.38 MHz to 16.76 MHz
16.76 MHz to 20 MHz
2.00 MHz to 4.2 MHz
7.60 MHz to 16.76 MHz
16.00 MHz to 20 MHz
4.00 MHz to 8.4 MHz
8.00 MHz to 8.38 MHz
16.00 MHz to 16.76 MHz
4.00 MHz to 4.19 MHz
Settable Selection Clock
2
C by using CLX0, SMC0, CL01, and CL00 before
(f
CLK
3
0
) Range
2
0
Normal mode (SMC0 bit = 0)
Fast mode (SMC0 bit = 1)
Fast mode (SMC0 bit = 1)
1
0
Operation Mode
CLX0
<0>