UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 645

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1.
Serial interface IIC0
Multiplier
Key interrupt
Reset function
Low-voltage detector
Regulator
DMA controller
Interrupt
BCD correction circuit
Register
RESF
LVIS
2.
3.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
These values vary depending on the reset source.
This value varies depending on the reset source and the option byte.
Reset Source
TRAP bit
WDRF bit
LVIRF bit
Table 19-2. Hardware Statuses After Reset Acknowledgment (3/3)
Shift register 0 (IIC0)
Control register 0 (IICC0)
Slave address register 0 (SVA0)
Clock select register 0 (IICCL0)
Function expansion register 0 (IICX0)
Status register 0 (IICS0)
Flag register 0 (IICF0)
Multiplication input data register A (MULA)
Multiplication input data register B (MULB)
Higher multiplication result storage register (MULOH)
Lower multiplication result storage register (MULOL)
Key return mode register (KRM)
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level select register (LVIS)
Regulator mode control register (RMC)
SFR address registers 0, 1 (DSA0, DSA1)
RAM address registers 0L, 0H, 1L, 1H (DRA0L, DRA0H, DRA1L, DRA1H)
Byte count registers 0L, 0H, 1L, 1H (DBC0L, DBC0H, DBC1L, DBC1H)
Mode control registers 0, 1 (DMC0, DMC1)
Operation control registers 0, 1 (DRC0, DRC1)
Request flag registers 0L, 0H, 1L, 1H, 2L, 2H (IF0L, IF0H, IF1L, IF1H,
IF2L, IF2H)
Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H (MK0L, MK0H, MK1L,
MK1H, MK2L, MK2H)
Priority specification flag registers 00L, 00H, 01L, 01H, 02L, 02H, 10L,
10H, 11L, 11H, 12L, 12H (PR00L, PR00H, PR01L, PR01H, PR10L,
PR10H, PR11L, PR11H, PR02L, PR02H, PR12L, PR12H)
External interrupt rising edge enable registers 0, 1 (EGP0, EGP1)
External interrupt falling edge enable registers 0, 1 (EGN0, EGN1)
BCD correction result register (BCDADJ)
Cleared (0)
Cleared (0EH)
RESET Input
CHAPTER 19 RESET FUNCTION
Hardware
Cleared (0)
Cleared (0EH)
User’s Manual U17893EJ8V0UD
Reset by POC
Reset by Execution of
Set (1)
Held
Held
Cleared (0EH)
Illegal Instruction
Held
Set (1)
Held
Cleared (0EH)
Reset by WDT
00H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
0000H
00H
00H
00H
0EH
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
Undefined
Acknowledgment
Status After Reset
Held
Held
Set (1)
Held
Reset by LVI
Note 2
Note 3
Note 2
Note 1
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