UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 727

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Conditional
skip
Instruction
Condition
al branch
CPU
control
Group
2.
3.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
3. n indicates the number of register banks (n = 0 to 3)
Mnemonic
BF
BTCLR
SKC
SKNC
SKZ
SKNZ
SKH
SKNH
SEL
NOP
EI
DI
HALT
STOP
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
When the program memory area is accessed.
This indicates the number of clocks “when condition is not met/when condition is met”.
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum.
register (CKC).
saddr.bit, $addr20
sfr.bit, $addr20
A.bit, $addr20
PSW.bit, $addr20
[HL].bit, $addr20
ES:[HL].bit, $addr20
saddr.bit, $addr20
sfr.bit, $addr20
A.bit, $addr20
PSW.bit, $addr20
[HL].bit, $addr20
ES:[HL].bit, $addr20
RBn
Operands
−
−
−
−
−
−
−
−
−
−
−
Table 27-5. Operation List (17/17)
CHAPTER 27 INSTRUCTION SET
Bytes
4
4
3
4
3
4
4
4
3
4
3
4
2
2
2
2
2
2
2
1
3
3
2
2
User’s Manual U17893EJ8V0UD
Note 1 Note 2
3/5
3/5
3/5
3/5
3/5
4/6
3/5
3/5
3/5
3/5
3/5
4/6
1
1
1
1
1
1
1
1
4
4
3
3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Clocks
6/7
7/8
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
PC ← PC + 4 + jdisp8 if (saddr).bit = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
PC ← PC + 3 + jdisp8 if (HL).bit = 0
PC ← PC + 4 + jdisp8 if (ES, HL).bit = 0
PC ← PC + 4 + jdisp8 if (saddr).bit = 1
then reset (saddr).bit
PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
PC ← PC + 4 + jdisp8 if (ES, HL).bit = 1
then reset (ES, HL).bit
Next instruction skip if CY = 1
Next instruction skip if CY = 0
Next instruction skip if Z = 1
Next instruction skip if Z = 0
Next instruction skip if (Z ∨ CY) = 0
Next instruction skip if (Z ∨ CY) = 1
RBS[1:0] ← n
No Operation
IE ← 1(Enable Interrupt)
IE ← 0(Disable Interrupt)
Set HALT Mode
Set STOP Mode
CPU
) selected by the system clock control
Operation
Z AC CY
×
Flag
×
725
×