UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 851

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Port
functions
Clock
generator
Function
PM0 to PM7,
PM9, PM11,
PM12, PM14:
Port mode
registers
P142/SCK20/
SCL20,
P143/SI20/RxD2
/SDA20,
P144/SO20/
TxD2
P145/TI07/TO07
P140/PCLBUZ0/
INTP6,
P141/PCLBUZ1/
INTP7
ADPC: A/D port
configuration
register
1-bit
manipulation
instruction for
port register n
(Pn)
CMC: Clock
operation mode
control register
CSC: Clock
operation status
control register
Details of
Function
To use P142/SCK20/SCL20, P143/SI20/RxD2/SDA20, or P144/SO20/TxD2 as a
general-purpose port, note the serial array unit 1 setting. For details, refer to the
following tables.
• Table 12-9 Relationship Between Register Settings and Pins (Channel 0 of Unit 1:
• Table 12-10 Relationship Between Register Settings and Pins (Channel 1 of Unit 1:
To use P145/TI07/TO07 as a general-purpose port, set bit 7 (TO07) of timer output
register 0 (TO0) and bit 7 (TOE07) of timer output enable register 0 (TOE0) to “0”,
which is the same as their default status setting.
To use P140/PCLBUZ0/INTP6 or P141/PCLBUZ1/INTP7 as a general-purpose port,
set bit 7 of clock output select registers 0 and 1 (CKS0, CKS1) to “0”, which is the
same as their default status settings.
Be sure to set bit 7 of PM0, bits 2 to 7 of PM3, bits 6 and 7 of PM5, bits 1 to 7 of
PM9, bits 2 to 7 of PM11, bits 1 to 7 of PM12, and bits 6 and 7 of PM14 to “1”.
Set the channel used for A/D conversion to the input mode by using port mode
registers 2 (PM2).
Do not set the pin set by ADPC as digital I/O by analog input channel specification
register (ADS).
When all pins of ANI0/P20 to ANI7/P27 are used as digital I/O (D), ADPC4 to ADPC0
can be set by either 01000 or 10000.
P20/ANI0 to P27/ANI7 are set as analog inputs in the order of P27/ANI7, …,
P20/ANI0 by the A/D port configuration register (ADPC). When using P20/ANI0 to
P27/ANI7 as analog inputs, start designing from P27/ANI7.
When a 1-bit manipulation instruction is executed on a port that provides both input
and output functions, the output latch value of an input port that is not subject to
manipulation may be written in addition to the targeted bit.
recommended to rewrite the output latch when switching a port from input mode to
output mode.
CMC can be written only once after reset release, by an 8-bit memory manipulation
instruction.
After reset release, set CMC before X1 or XT1 oscillation is started as set by the
clock operation status control register (CSC).
Be sure to set AMPH to 1 if the X1 clock oscillation frequency exceeds 10 MHz.
It is recommended to set the default value (00H) to CMC after reset release, even
when the register is used at the default value, in order to prevent malfunctioning
during a program loop.
After reset release, set the clock operation mode control register (CMC) before
starting X1 oscillation as set by MSTOP or XT1 oscillation as set by XTSTOP.
To start X1 oscillation as set by MSTOP, check the oscillation stabilization time of the
X1 clock by using the oscillation stabilization time counter status register (OSTC).
Do not stop the clock selected for the CPU/peripheral hardware clock (f
CSC register.
CSI20, UART2 Transmission, IIC20)
UART2 Reception)
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
Cautions
Therefore, it is
CLK
) with the
p.133
p.133
p.133
p.138
p.143
p.143
p.143
p.143
p.150
p.155
p.155
p.155
p.155
p.156
p.156
p.156
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