UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 857

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Operation of
timer array
unit as
independent
channel
Operation
of plural
channels of
timer array
unit
Real-time
counter
Function
Input pulse
interval
measurement
Input signal
high-/low-level
width
measurement
PWM function
One-shot pulse
output function
Multiple PWM
output function
PER0:
Peripheral
enable register 0
RTCC0: Real-
time counter
control register 0
RTCC1: Real-
time counter
control register 1
RTCC2: Real-
time counter
control register 2
Details of
Function
The timing of loading of TDR0n of the master channel is different from that of TDR0m
of the slave channel. If TDR0n and TDR0m are rewritten during operation, therefore,
an illegal waveform is output. Rewrite the TDR0n after INTTM0n is generated and the
TDR0m after INTTM0m is generated.
To rewrite both TDR0n of the master channel and TDR0p of the slave channel 1, write
access is necessary at least twice. Since the values of TDR0n and TDR0p are
loaded to TCR0n and TCR0p after INTTM0n is generated from the master channel, if
rewriting is performed separately before and after generation of INTTM0n from the
master channel, the TO0p pin cannot output the expected waveform. To rewrite both
TDR0n of the master and TDR0p of the slave, be sure to rewrite both the registers
immediately after INTTM0n is generated from the master channel. (This applies also
to TDR0q of the slave channel 2.)
When using the real-time counter, first set RTCEN to 1, while oscillation of the
subsystem clock (f
time counter is ignored, and, even if the register is read, only the default value is read.
If RCLOE0 and RCLOE1 are changed when RTCE = 1, glitches may occur in the
32.768 kHz and 1 Hz output signals.
The RIFG and WAFG flags may be cleared when the RTCC1 register is written by
using a 1-bit manipulation instruction. Use, therefore, an 8-bit manipulation instruction
in order to write to the RTCC1 register. To prevent the RIFG and WAFG flags from
being cleared during writing, disable writing by setting “1” to the corresponding bit.
When the value may be rewritten because the RIFG and WAFG flags are not being
used, the RTCC1 register may be written by using a 1-bit manipulation instruction.
Change ICT2, ICT1, and ICT0 when RINTE = 0.
When the output from RTCDIV pin is stopped, the output continues after a maximum
of two clocks of f
output is stopped immediately after entering the high level, a pulse of at least one
clock width of f
After the real-time counter starts operating, the output width of the RTCDIV pin may
be shorter than as set during the first interval period.
The TI0n pin input is sampled using the operating clock selected with the CKS0n bit
of the TMR0n register, so an error equal to the number of operating clocks occurs.
The TI0n pin input is sampled using the operating clock selected with the CKS0n bit
of the TMR0n register, so an error equal to the number of operating clocks occurs.
To rewrite both TDR0n of the master channel and TDR0m of the slave channel, a
write access is necessary two times. The timing at which the values of TDR0n and
TDR0m are loaded to TCR0n and TRC0m is upon occurrence of INTTM0n of the
master channel. Thus, when rewriting is performed split before and after occurrence
of INTTM0n of the master channel, the TO0m pin cannot output the expected
waveform. To rewrite both TDR0n of the master and TDR0m of the slave, therefore,
be sure to write both the registers immediately after INTTM0n is generated from the
master channel.
Be sure to clear bit 1 of the PER0 register to 0.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
XT
XT
may be generated.
SUB
and enters the low level. While 512 Hz is output, and when the
) is stable. If RTCEN = 0, writing to a control register of the real-
Cautions
p.244
p.248
p.252
p.259
p.266
p.276
p.276
p.277
p.279
p.280
p.280
p.280
(10/34)
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