UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 366

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
364
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
SMRmn
Symbol
Remark
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11),
F0154H, F0155H (SMR12), F0156H, F0157H (SMR13)
For successive transmission, the next transmit data is written by setting MDmn0 to 1 when SDRmn data has run
out.
mn0
mn2
mn0
CKS
SIS
MD
MD
mn
15
0
1
0
0
1
1
0
1
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
Falling edge is detected as the start bit.
The input communication data is captured as is.
Rising edge is detected as the start bit.
The input communication data is inverted and captured.
Transfer end interrupt
Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
CCS
mn1
MD
mn
14
0
1
0
1
Figure 12-6. Format of Serial Mode Register mn (SMRmn) (2/2)
CSI mode
UART mode
Simplified I
Setting prohibited
13
0
12
0
2
C mode
Controls inversion of level of receive data of channel n in UART mode
CHAPTER 12 SERIAL ARRAY UNIT
11
0
User’s Manual U17893EJ8V0UD
10
0
Selection of interrupt source of channel n
Setting of operation mode of channel n
9
0
STS
mn
8
After reset: 0020H
7
0
mn0
SIS
6
5
1
R/W
4
0
3
0
mn2
MD
2
mn1
MD
1
mn0
MD
0