UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 62

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UPD78F1152AGC-GAD-AX

Manufacturer Part Number
UPD78F1152AGC-GAD-AX
Description
MCU 16BIT 78K0R/KX3 80-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1152AGC-GAD-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1152AGC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
<R>
3.1.6 Data memory addressing
the register or memory relevant to the execution of instructions.
78K0R/KF3, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are
available for use. Figures 3-7 to 3-11 show correspondence between data memory and addressing.
60
F F F 2 0 H
F F F 0 0 H
F 0 8 0 0 H
F F F F F H
F F F 1 F H
F F E F F H
F F E E 0 H
F F E D F H
F F E 2 0 H
F F E 1 F H
F E F 0 0 H
F E E F F H
F 1 0 0 0 H
F 0 F F F H
F 0 7 F F H
F 0 0 0 0 H
E F F F F H
1 0 0 0 0 H
0 F F F F H
0 E F 0 0 H
0 E E F F H
0 1 0 0 0 H
0 0 F F F H
0 0 0 0 0 H
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
Figure 3-7. Correspondence Between Data Memory and Addressing (
Special function register (2nd SFR)
General-purpose register
Special function register (SFR)
Flash memory 64 KB
Mirrored area 55.75 KB
32 bytes
Mirror area
Reserved
Reserved
256 bytes
55.75 KB
RAM
4 KB
2 KB
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17893EJ8V0UD
SFR addressing
Register addressing
MAA = 0
Mirror
Short direct
addressing
μ
PD78F1152, 78F1152A)
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing

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