UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 595

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remarks 1. n: DMA channel number (n = 0, 1)
Caution
• Procedure for forcibly terminating the DMA
transfer for one channel if both channels are used
2. 1 clock: 1/f
In example 3, the system is not required to wait two clock cycles after DWAITn is set to 1. In
addition, the system does not have to wait two clock cycles after clearing DSTn to 0, because
more than two clock cycles elapse from when DSTn is cleared to 0 to when DENn is cleared to
0.
Figure 15-13. Forced Termination of DMA Transfer (2/2)
DWAIT0 = 1
DWAIT1 = 1
DWAIT0 = 0
DWAIT1 = 0
CLK
DSTn = 0
DENn = 0
(f
CLK
: CPU clock)
CHAPTER 15 DMA CONTROLLER
User’s Manual U17893EJ8V0UD
Example 3
• Procedure for forcibly terminating the DMA
transfer for both channels if both channels are used
DWAIT0 = 1
DWAIT1 = 1
DWAIT0 = 0
DWAIT1 = 0
DST0 = 0
DST1 = 0
DEN0 = 0
DEN1 = 0
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