UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 529

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SDA0
SCL0
Remark
Communication reservations are accepted via the timing shown in Figure 13-22. After bit 1 (STD0) of IIC
status register 0 (IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC
control register 0 (IICC0) to 1 before a stop condition is detected.
Figure 13-23 shows the communication reservation protocol.
SDA0
SPD0
SCL0
STD0
Hardware processing
Program processing
1
IIC0:
STT0:
STD0: Bit 1 of IIC status register 0 (IICS0)
SPD0: Bit 0 of IIC status register 0 (IICS0)
2
Figure 13-22. Timing for Accepting Communication Reservations
3
Bit 1 of IIC control register 0 (IICC0)
IIC shift register 0
STT0 = 1
Communi-
cation
reservation
4
Figure 13-21. Communication Reservation Timing
Standby mode (Communication can be reserved
5
by setting STT to 1 during this period.)
CHAPTER 13 SERIAL INTERFACE IIC0
6
User’s Manual U17893EJ8V0UD
7
Generate by master device with bus mastership
8
9
Set SPD0
and
INTIIC0
Write to
IIC0
Set
STD0
1
2
3
4
5
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6