UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 162

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

160
Address: FFFA3H
Symbol
OSTS
Remark f
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the
Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS)
OSTS2
7
0
0
0
0
0
1
1
1
1
After reset: 07H
2. Setting the oscillation stabilization time to 20
3. To change the setting of the OSTS register, be sure to confirm that the counting
4. Do not change the value of the OSTS register during the X1 clock oscillation
5. The oscillation stabilization time counter counts up to the oscillation
6. The X1 clock oscillation stabilization wait time does not include the time until
X
: X1 clock oscillation frequency
OSTS register before executing the STOP instruction.
operation of the OSTC register has been completed.
stabilization time.
stabilization time set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than or equal to the count value which is to be checked by the OSTC
register.
clock oscillation starts (“a” below).
OSTS1
6
0
0
0
1
1
0
0
1
1
X1 pin voltage
waveform
CHAPTER 5 CLOCK GENERATOR
• If the X1 clock starts oscillation while the internal high-speed
• If the STOP mode is entered and then released while the internal
R/W
OSTS0
oscillation clock or subsystem clock is being used as the CPU
clock.
high-speed oscillation clock is being used as the CPU clock with
the X1 clock oscillating. (Note, therefore, that only the status up to
the oscillation stabilization time set by OSTS is set to OSTC after
the STOP mode is released.)
User’s Manual U17893EJ8V0UD
5
0
0
1
0
1
0
1
0
1
STOP mode release
2
2
2
2
2
2
2
2
8
9
10
11
13
15
17
18
/f
/f
/f
/f
/f
/f
/f
/f
X
X
X
X
X
X
X
X
4
0
a
Oscillation stabilization time selection
3
0
25.6
51.2
102.4
204.8
819.2
3.27 ms
13.11 ms
26.21 ms
f
X
μ
μ
μ
μ
μ
= 10 MHz
s
s
OSTS2
μ
s
s
s
s or less is prohibited.
2
OSTS1
Setting prohibited
25.6
51.2
102.4
409.6
1.64 ms
6.55 ms
13.11 ms
1
f
X
μ
μ
μ
μ
= 20 MHz
s
s
s
s
OSTS0
0