UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 640

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

638
(when X1 oscillation is selected)
(when X1 oscillation is selected)
Note Set P130 to high-level output by software.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
Note Set P130 to high-level output by software.
Caution A watchdog timer internal reset resets the watchdog timer.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
High-speed system clock
High-speed system clock
Figure 19-3. Timing of Reset Due to Execution of Illegal Instruction or Watchdog Timer Overflow
Internal reset signal
Internal reset signal
Internal high-speed
Internal high-speed
Execution of illegal
oscillation clock
oscillation clock
watchdog timer
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
(except P130)
(except P130)
CPU status
CPU status
instruction/
overflow
Port pin
Port pin
RESET
Port pin
Port pin
(P130)
(P130)
Normal operation
Normal operation
Figure 19-2. Timing of Reset by RESET Input
CHAPTER 19 RESET FUNCTION
(5 s (MAX.))
User’s Manual U17893EJ8V0UD
μ
Delay
(oscillation stop)
(oscillation stop)
(100 ns (TYP.))
Reset period
Reset period
(5 s (MAX.))
μ
Delay
accuracy stabilization
accuracy stabilization
Wait for oscillation
Wait for oscillation
Reset processi n g
(61 to 162 s)
μ
Hi-Z
Hi-Z
Reset processing
(1.92 to 6.17 ms)
Starting X1 oscillation is specified by software.
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Normal operation
(internal high-speed oscillation clock)
Note
Note