UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 894

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

892
3rd edition
Edition
Changes of setting of (b) Serial output enable register m (SOEm) in Figure 12-74
Example of Contents of Registers for UART Reception of UART (UART0,
UART1, UART2, UART3)
Change of Figure 12-89 Flowchart of Address Field Transmission
Change of Figure 12-92 Flowchart of Data Transmission
Addition of Caution 2 to 13.3 (1) Peripheral enable register 0 (PER0)
Change of description of 13.5.4 (2) Selection clock setting method on the slave
side
Addition of description to <1> and <3> in 15.4.1 Operation procedure
Addition of description to 15.5.5 Forced termination by software
Additions of description and Note to 15.6 (1) Priority of DMA
A
• Figure 18-4 HALT Mode Release by Reset
• Figure 18-6 STOP Mode Release by Interrupt Request Generation
• Figure 18-7 STOP Mode Release by Reset
Change of Figure 18-5 Operation Timing When STOP Mode Is Released
(When Unmasked Interrupt Request Is Generated)
Change of Figure 19-2 Timing of Reset by RESET Input
Change of Figure 19-3 Timing of Reset Due to Watchdog Timer Overflow
Change of Figure 19-4 Timing of Reset in STOP Mode by RESET Input
Addition of reset processing time to Figure 20-2 Timing of Generation of Internal
Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector
Addition of 20.4 Caution for Power-on-Clear Circuit
Addition of operation stabilization time
Change of Caution 2 in Figure 21-3 Format of Low-Voltage Detection Level
Select Register (LVIS)
Addition of 21.5 Caution for Low Voltage Detector
Change of description of 23.1.1 (2) 000C1H/010C1H
Change of Figure 23-2 Format of User Option Byte(000C1H/010C1H)
Change of Figure 23-4 Format of On-chip Debug Option Byte(000C3H/010C3H)
Addition of description to 24. 4.1 (3) During writing by self programming
Addition of description to 24.5 (1) Background event control register (BECTL)
Addition of 24.6 Programming Method
Addition of 24.7 Security Settings
Addition of 24.8 Flash Memory Programming by Self-programming
Addition of chapter
Deletion of description of BCD correction carry register (BCDCY bit), etc.
Absolute Maximum Ratings
• Addition of regulator voltage (REGC)
• Change of Input voltage and output voltage
Addition of MIN. value and MAX. value in XT1 Oscillator Characteristics
dditions of reset processing time and clock supply stop time to the following figures
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
Description
CHAPTER 12 SERIAL
ARRAY UNIT
CHAPTER 13 SERIAL
INTERFACE IIC0
CHAPTER 15 DMA
CONTROLLER
CHAPTER 18
STANDBY FUNCTION
CHAPTER 19 RESET
FUNCTION
CHAPTER 20 POWER-
ON-CLEAR CIRCUIT
CHAPTER 21 LOW-
VOLTAGE DETECTOR
CHAPTER 23 OPTION
BYTE
CHAPTER 24 FLASH
MEMORY
CHAPTER 25 ON-CHIP
DEBUGGING
CHAPTER 26 BCD
CORRECTION CIRCUIT
CHAPTER 28
ELECTRICAL
SPECIFICATIONS
(TARGET)
Chapter
(8/20)