UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 404

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
402
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
Remark
Writing 1 to MDmn0 bit
Figure 12-39. Flowchart of Master Reception (in Continuous Reception Mode)
have elapsed.
<1> to <8> in the figure correspond to <1> to <8> in Figure 12-38 Timing Chart of Master
Reception (in Continuous Reception Mode).
<3>
<6>
Yes
No
SMRmn, SCRmn:
SDRmn[15:9]:
SOm
<2>
<4>
<5>
<7>
<8>
CHAPTER 12 SERIAL ARRAY UNIT
Writing dummy data to SIOp
Clearing SAU1EN and SAU0EN
Setting SAU1EN and SAU0EN
Reading receive data from
Reading receive data from
User’s Manual U17893EJ8V0UD
Starting CSI communication
Clearing 0 to MDmn0 bit
Setting transfer rate by
bits of PER0 register to 1
Communication continued?
bits of PER0 register to 0
End of communication
Writing 1 to SSmn bit
Writing 1 to STmn bit
SIOp (=SDRmn[7:0])
SIOp (=SDRmn[7:0])
Port manipulation
The following is the last
Buffer empty interrupt
Transfer end interrupt
(=SDRmn[7:0])
SPSm register
Setting communication
Setting transfer rate
Setting output and SCKp output
No
TSFmn = 1?
Yes
Yes
receive data?
generated?
generated?
Yes
No
No
No
Yes
Perform initial setting when SEmn = 0.
<1> Select the buffer empty interrupt.