UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 873
UPD78F1152AGC-GAD-AX
Manufacturer Part Number
UPD78F1152AGC-GAD-AX
Description
MCU 16BIT 78K0R/KX3 80-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1152AGC-GAD-AX.pdf
(908 pages)
Specifications of UPD78F1152AGC-GAD-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1152AGC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Low-
voltage
detector
Function
LVIS: Low-
voltage detection
level select
register
Used as reset
(when detecting
level of supply
voltage (V
(LVIOFF = 1)
Used as reset
(when detecting
level of input
voltage from
external input pin
(EXLVI))
Details of
Function
DD
))
Change the LVIS value with either of the following methods.
• When changing the value after stopping LVI
<1> Stop LVI (LVION = 0).
<2> Change the LVIS register.
<3> Set to the mode used as an interrupt (LVIMD = 0).
<4> Mask LVI interrupts (LVIMK = 1).
<5> Enable LVI operation (LVION = 1).
<6> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
• When changing the value after setting to the mode used as an interrupt (LVIMD =
<1> Mask LVI interrupts (LVIMK = 1).
<2> Set to the mode used as an interrupt (LVIMD = 0).
<3> Change the LVIS register.
<4> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
When an input voltage from the external input pin (EXLVI) is detected, the detection
voltage (V
<1> must always be executed.
immediately after the processing in <4>.
If supply voltage (V
reset signal is not generated.
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
<1> must always be executed.
immediately after the processing in <3>.
If input voltage from external input pin (EXLVI) ≥ detection voltage (V
(TYP.)) when LVIMD is set to 1, an internal reset signal is not generated.
Input voltage from external input pin (EXLVI) must be EXLVI < V
0)
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
because an LVIIF flag may be set when LVI operation is enabled.
because an LVIIF flag may be set when the LVIS register is changed.
APPENDIX B LIST OF CAUTIONS
EXLVI
User’s Manual U17893EJ8V0UD
) is fixed. Therefore, setting of LVIS is not necessary.
DD
) ≥ detection voltage (V
When LVIMK = 0, an interrupt may occur
When LVIMK = 0, an interrupt may occur
Cautions
LVI
) when LVIMD is set to 1, an internal
DD
.
EXLVI
= 1.21 V
μ
s
p.656
p.656
p.658
p.658
p.660
p.662
p.662
p.662
(26/34)
871
Page
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