UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 399

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Operation procedure
Caution
Remark
Even after communication is stopped, the pin level is retained. To resume the operation, re-set the
SOm register (see Figure 12-35 Procedure for Resuming Master Reception).
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Setting SMRmn register
Setting SCRmn register
Setting SDRmn register
Starting communication
Writing to SSm register
Stopping communication
Setting SPSm register
Setting PER0 register
Setting SOm register
Starting initial setting
Starting setting to stop
Setting STm register
Figure 12-33. Initial Setting Procedure for Master Reception
Setting port
Figure 12-34. Procedure for Stopping Master Reception
CHAPTER 12 SERIAL ARRAY UNIT
User’s Manual U17893EJ8V0UD
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate.
Manipulate the CKOmn bit and set an
initial output level.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set dummy data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
Release the serial array unit from the
reset status and start clock supply.
Write 1 to the STmn bit of the target
channel.
Stop communication in midway.
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