UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 884

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark “Classification” in the above table classifies revisions as follows.
882
CHAPTER 12 SERIAL ARRAY UNIT (continuation)
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CHAPTER 13 SERIAL INTERFACE IIC0
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CHAPTER 15 DMA CONTROLLER
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(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Change of Figure 12-35. Procedure for Resuming Master Reception
Change of Figure 12-37. Flowchart of Master Reception (in Single-Reception Mode)
Addition of Figure 12-38. Timing Chart of Master Reception (in Continuous Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
Addition of Figure 12-39. Flowchart of Master Reception (in Continuous Reception Mode)
Change of Figure 12-51. Procedure for Resuming Slave Transmission
Change of Figure 12-53. Flowchart of Slave Transmission (in Single-Transmission Mode)
Change of Figure 12-55. Flowchart of Slave Transmission (in Continuous Transmission
Mode)
Change of Figure 12-56. Example of Contents of Registers for Slave Reception of 3-Wire
Serial I/O (CSI00, CSI01, CSI10, CSI20)
Change of Figure 12-59. Procedure for Resuming Slave Reception
Change of Figure 12-61. Flowchart of Slave Reception (in Single-Reception Mode)
Addition of Caution to Figure 12-62. Example of Contents of Registers for Slave
Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20)
Addition of Caution to Figure 12-63. Initial Setting Procedure for Slave Transmission/Reception
Change of Figure 12-65. Procedure for Resuming Slave Transmission/Reception
Change of Figure 12-67. Flowchart of Slave Transmission/Reception (in Single-
Transmission/Reception Mode)
Change of Figure 12-69. Flowchart of Slave Transmission/Reception (in Continuous
Transmission/Reception Mode)
Change of Figure 12-79. Example of Contents of Registers for UART Reception of UART
(UART0, UART1, UART2, UART3) (1/2)
Change of Figure 12-82. Procedure for Resuming UART Reception
Change of Figure 12-84. Flowchart of UART Reception
Change of 12.7 Operation of Simplified I
Change of transfer rate in 12.7.1 Address field transmission
Change of transfer rate in 12.7.2 Data transmission
Change of error detection flag and transfer rate in 12.7.3 Data reception
Addition of Caution to 12.7.5 Calculating transfer rate
Change of Remark in 12.7.5 Calculating transfer rate
Addition of Figure 12-105. Processing Procedure in Case of Parity Error or Overrun Error
Change of description of STT0 bit in Figure 13-6. Format of IIC Control Register 0 (IICC0) (3/4)
Addition of Note to Figure 15-4. Format of DMA Mode Control Register n (DMCn) (1/2)
Change of description in 15.5.1 CSI consecutive transmission
Change of description in Figure 15-7. Setting Example of CSI Consecutive Transmission
Addition of 15.5.2 CSI master reception
Addition of 15.5.3 CSI transmission/reception
Change of description in 15.5.6 Holding DMA transfer pending by DWAITn
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
2
C (IIC10, IIC20) Communication
Description
Classification
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