UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 372

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

370
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03),
SSRmn
Symbol
Remark
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11),
F0144H, F0145H (SSR12), F0146H, F0147H (SSR13)
This is a cumulative flag and is not cleared until 1 is written to the FECTmn bit of the SIRmn register.
This is a cumulative flag and is not cleared until 1 is written to the PECTmn bit of the SIRmn register.
This is a cumulative flag and is not cleared until 1 is written to the OVCTmn bit of the SIRmn register.
OVF
PEF
FEF
mn
mn
mn
15
0
1
0
1
0
1
0
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
No error occurs.
A framing error occurs during UART reception.
Error does not occur.
A parity error occurs during UART reception or ACK is not detected during I
No error occurs.
An overrun error occurs.
14
0
<Framing error cause>
A framing error occurs if the stop bit is not detected upon completion of UART reception.
<Parity error cause>
• A parity error occurs if the parity of transmit data does not match the parity bit on completion of UART
• ACK is not detected if the ACK signal is not returned from the slave in the timing of ACK reception
<Causes of overrun error>
• Receive data stored in the SDRmn register is not read and transmit data is written or the next receive
• Transmit data is not ready for slave transmission or reception in the CSI mode.
Figure 12-9. Format of Serial Status Register mn (SSRmn) (2/2)
reception.
during I
data is written.
13
0
2
C transmission.
12
0
CHAPTER 12 SERIAL ARRAY UNIT
11
0
User’s Manual U17893EJ8V0UD
10
0
Framing error detection flag of channel n
Overrun error detection flag of channel n
Parity error detection flag of channel n
9
0
8
0
After reset: 0000H
7
0
TSF
mn
6
BFF
mn
5
R
2
4
0
C transmission.
3
0
FEF
mn
2
PEF
mn
1
OVF
mn
0