UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 865

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Registers
controlling
serial array
unit
Operation
stop mode
3-wire serial I/O
(CSI00, CSI01,
CSI10, CSI20)
communication
Function
SOEm: Serial
output enable
register m
SOm: Serial
output register m
SOLm: Serial
output level
register m
ISC: Input switch
control register
NFEN0: Noise
filter enable
register 0
Stopping the
operation by
units
Master
transmission
Master transmission
(in continuous
transmission mode)
Master reception After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
Master Reception
(in Continuous
Reception Mode)
Master
transmission/
reception
Master
transmission/
reception (in
continuous
transmission/
reception mode)
Slave
transmission
Slave transmission
(in continuous
transmission mode)
Slave reception
Slave
transmission/
reception
Details of
Function
The MDmn0 bit can be rewritten even during operation.
The MDmn0 bit can be rewritten even during operation.
Be sure to clear bits 15 to 3 of SOE0, and bits 15 to 3 and 1 of SOE1 to “0”.
Be sure to set bits 11 and 3 of SO0, and bits 11 to 9, 3, and 1 of SO1 to “1”. And be
sure to clear bits 15 to 12 and 7 to 4 of SOm to “0”.
Be sure to clear bits 15 to 3 and 1 to “0”.
Be sure to clear bits 7 to 2 to “0”.
Be sure to clear bits 7, 5, 3, and 1 to “0”.
If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and,
even if the register is read, only the default value is read (except for input switch
control register (ISC), noise filter enable register (NFEN0), port input mode registers
(PIM0, PIM4, PIM14), port output mode registers (POM0, POM4, POM14), port mode
registers (PM0, PM1, PM4, PM14), and port registers (P0, P1, P4, P14)).
Be sure to clear bit 1 of the PER0 register to 0.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
before the transfer end interrupt of the last transmit data.
clocks have elapsed.
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before receive of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last receive data.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
However, rewrite it before transfer of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last transmit data.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
The MDmn0 bit can be rewritten even during operation. However, rewrite it before
transfer of the last bit is started.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
Be sure to set transmit data to the SlOp register before the clock from the master is
started.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
Cautions
392, 394
400, 402
408, 410
417, 419
432, 434
p.375
p.376
p.377
p.378
p.379
p.382
p.382
pp.388,
p.393
pp.397,
p.401
pp.405,
p.409
pp.413,
p.418
pp.422,
425
pp.427,
428
pp.428,
(18/34)
863
Page