UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 905

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7th edition
Edition
Change of Figure 12-93 Timing Chart of Data Transmission
Addition of Note to 12.7.3 Data reception
Change of Figure 12-96 Timing Chart of Data Reception
Change of Figure 12-97 Flowchart of Data Reception and change of Caution
Change of Figure 12-98 Timing Chart of Stop Condition Generation
Change of Note 2 in Table 12-4 Selection of Operation Clock
Change of Cautions 1 in Figure 13-5. Format of Peripheral Enable Register 0
(PER0)
Change of Note in Figure 13-6 Format of IIC Control Register 0 (IICC0)
Change of Table 13-2 Selection Clock Setting
Change of Table 13-3 Selection Clock Setting
Change of Table 13-5 Extension Code Bit Definitions
Change of Figure 13-24 Master Operation in Single-Master System
Change of Figure 13-25 Master Operation in Multi-Master System
Change of Figure 13-26 Slave Operation Flowchart
Change of Figures 13-28 and 13-29
Change of Figure 15-5 Format of DMA Operation Control Register n (DRCn)
Addition of Note to Table 15-2 Response Time of DMA Transfer
Change of description in 16.2 Interrupt Sources and Configuration
Change of Table 16-1 Interrupt Source List
Change of Cautions 2 in 17.3 (1) Key return mode register (KRM)
Change of Note in Figure 18-3 HALT Mode Release by Interrupt Request
Generation
Change of Figure 18-5 Operation Timing When STOP Mode Is Released
(Release by Unmasked Interrupt Request)
Addition of Note to Figure 18-6 STOP Mode Release by Interrupt Request
Generation
Change of Table 19-1. Operation Statuses During Reset Period
Deletion of Note in 20.1 Functions of Power-on-Clear Circuit
Deletion of Note in 20.3 Operation of Power-on-Clear Circuit
Deletion of Note 6 in (1) When LVI is OFF upon power application (option byte:
LVIOFF = 1) in Figure 20-2 Timing of Generation of Internal Reset Signal by
Power-on-Clear Circuit and Low-Voltage Detector
Deletion of Note 3 in (2) When LVI is ON upon power application (option byte:
LVIOFF = 0) in Figure 20-2 Timing of Generation of Internal Reset Signal by
Power-on-Clear Circuit and Low-Voltage Detector
Deletion of Note in 21.1 Functions of Low-Voltage Detector
Deletion of Note 2 in Figure 21-3 Format of Low-Voltage Detection Level Select
Register (LVIS)
Deletion of Note in 21.4 Operation of Low-Voltage Detector
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
Description
CHAPTER 12 SERIAL
ARRAY UNIT
CHAPTER 13 SERIAL
INTERFACE IIC0
CHAPTER 15 DMA
CONTROLLER
CHAPTER 16
INTERRUPT
FUNCTIONS
CHAPTER 17 KEY
INTERRUPT
FUNCTION
CHAPTER 18
STANDBY FUNCTION
CHAPTER 19 RESET
FUNCTION
CHAPTER 20 POWER-
ON-CLEAR CIRCUIT
CHAPTER 21 LOW-
VOLTAGE DETECTOR
Chapter
(19/20)
903