UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 895

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3rd edition
4th edition
Edition
DC characteristics
• Change of Condition and Note 1 in Output current, high (I
• Change of Condition and Note 2 in Output current, low (I
• Change of Condition of Input voltage, high (V
• Change of Condition of Input voltage, low (V
• Change of Condition of Output voltage, low (V
• Addition of Supply current
• Addition of Watchdog Timer operating current (I
• Addition of A/D Converter operating current (I
• Addition of D/A Converter operating current(I
• Addition of DMA Controller operating current (I
• Addition of LVI operating current (I
Change of MIN. value of Conversion time (t
Addition of POC Circuit Characteristics
Addition of Supply Voltage Rise Time
Addition of LVI Circuit Characteristics
Addition of Data Memory STOP Mode Low Supply Voltage Data Retention
Characteristics
Revision of chapter
Deletion of target from the capacitance value of the capacitor connected to the REGC
pin
Change of description in 2.2.18 REGC
Modification of P60 to P64, P110 and P111 in Table 2-2 Connection of Unused
Pins
Modification of 12-D to 12-G in Figure 2-1 Pin I/O Circuit List (2/2)
Addition (address change) of the BCDADJ register to Table 3-6 Extended SFR (2nd
SFR) List (1/5)
Change of Figure 4-6 Block Diagram of P05 and P06
Change of Figure 4-28 Block Diagram of P110 and P111
Change of Figure 4-42 Bit Manipulation Instruction (P10)
Change of Caution 2 in Figure 5-6 Format of System Clock Control Register
(CKC)
Change of description in 5.3 (8) Internal high-speed oscillator trimming register
(HIOTRM) and addition of Caution
Change of Figure 5-9 Format of Internal High-Speed Oscillator Trimming
Register (HIOTRM) and addition of Caution
Change of Figure 5-13 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1))
Addition of Note to Figure 6-5 Format of Timer Clock Select Register 0 (TPS0)
Change of Table 6-3 OVF Bit Operation and Set/Clear Conditions in Each
Operation Mode and addition of Remark
Addition of Caution 2 to Figure 6-18 Format of Timer Output Register 0 (TO0)
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
LVI
Description
)
CONV
IL2
DAC
IH2
ADC
)of A/D Converter Characteristics
OL1
)
DMA
)
WDT
)
)
)
)
)
OL1
OH1
)
)
CHAPTER 28
ELECTRICAL
SPECIFICATIONS
(TARGET)
APPENDIX A
DEVELOPMENT TOOLS
Throughout
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 TIMER
ARRAY UNIT
Chapter
(9/20)
893