UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 874

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

872
Low-
voltage
detector
Function
Used as interrupt
(when detecting
level of supply
voltage (V
(LVIOFF = 0)
Used as interrupt
(when detecting
level of input
voltage from
external input pin
(EXLVI))
Cautions for low-
voltage detector
Details of
Function
DD
))
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the
LVIRF flag may become 1 from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 19 RESET FUNCTION.
The input voltage from the external input pin (EXLVI) must be EXLVI < V
In a system where the supply voltage (V
vicinity of the LVI detection voltage (V
how the low-voltage detector is used.
Operation example 1: When used as reset
The system may be repeatedly reset and released from the reset status.
The time from reset release through microcontroller operation start can be set
arbitrarily by the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each
system by means of a software counter that uses a timer, and then initialize the ports
(see Figure 21-11).
Operation example 2: When used as interrupt
Interrupt requests may be generated frequently.
Take the following action.
<Action>
Confirm that “supply voltage (V
falling edge of V
the rising edge of V
(LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of interrupt
request flag register 0L (IF0L) to 0.
For a system with a long supply voltage fluctuation period near the LVI detection
voltage, take the above action after waiting for the supply voltage fluctuation time.
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
DD
, or “supply voltage (V
DD
, in the servicing routine of the LVI interrupt by using bit 0
DD
) ≥ detection voltage (V
Cautions
LVI
DD
), the operation is as follows depending on
) < detection voltage (V
DD
) fluctuates for a certain period in the
LVI
)” when detecting the
LVI
)” when detecting
DD
.
μ
s
p.666
p.666
p.668
pp.670
to 673
(27/34)
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