UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 432

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
430
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
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Figure 12-65. Procedure for Resuming Slave Transmission/Reception
Changing setting of SOEm register
Changing setting of SOEm register
Changing setting of SPSm register
Changing setting of SMRmn register
Changing setting of SCRmn register
Changing setting of SOm register
Manipulating target for communication
Starting target for communication
Starting setting for resumption
Starting communication
Writing to SSm register
Clearing error flag
Port manipulation
Port manipulation
CHAPTER 12 SERIAL ARRAY UNIT
User’s Manual U17893EJ8V0UD
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
Enable data output of the target channel
by setting a port register and a port mode
register.
Start the target for communication.
Stop the target for communication or wait
until the target completes its operation.
Disable data output of the target channel
by setting a port register and a port
mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Set the SOEm register and stop the
output of the target channel.
Manipulate the SOmn bit and set an
initial output level.
Set the SOEm register and enable the
output of the target channel.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.