UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 324

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UPD78F1152AGC-GAD-AX

Manufacturer Part Number
UPD78F1152AGC-GAD-AX
Description
MCU 16BIT 78K0R/KX3 80-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1152AGC-GAD-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1152AGC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(6) A/D port configuration register (ADPC)
322
Symbol
Address: F0017H
ADPC
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode registers 2
This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port.
ADPC can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
ADPC4
2. Do not set the pin that is set by ADPC as digital I/O by ADS.
3. When all pins of ANI0/P20 to ANI7/P27 are used as digital I/O (D), ADPC4 to ADPC0 can be set
4. P20/ANI0 to P27/ANI7 are set as analog inputs in the order of P27/ANI7, …, P20/ANI0 by the
7
0
0
0
0
0
0
0
0
0
0
1
(PM2).
by either 01000 or 10000.
A/D port configuration register (ADPC). When using P20/ANI0 to P27/ANI7 as analog inputs,
start designing from P27/ANI7.
After reset: 10H
Figure 10-10. Format of A/D Port Configuration Register (ADPC)
ADPC3
6
0
0
0
0
0
0
0
0
0
1
0
Other than above
R/W
ADPC2
5
0
0
0
0
0
1
1
1
1
0
0
CHAPTER 10 A/D CONVERTER
User’s Manual U17893EJ8V0UD
ADPC1
ADPC4
4
0
0
1
1
0
0
1
1
0
0
ADPC0
ADPC3
0
1
0
1
0
1
0
1
0
0
3
ANI7
/P27
Setting prohibited
D
D
A
A
A
A
A
A
A
A
Analog Input (A)/digital I/O (D) switching
ADPC2
ANI6
/P26
2
D
D
D
A
A
A
A
A
A
A
ANI5
/P25
D
D
D
D
A
A
A
A
A
A
ANI4
/P24
ADPC1
A
A
A
A
A
D
D
D
D
D
1
ANI3
/P23
A
A
A
A
D
D
D
D
D
D
ANI2
/P22
A
A
A
D
D
D
D
D
D
D
ADPC0
ANI1
/P21
A
A
D
D
D
D
D
D
D
D
0
ANI0
/P20
D
D
D
D
D
D
D
D
D
A

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