UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 601

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Maskable
Software
Reset
Interrupt
Type
Notes 1.
2.
3.
4.
Priority
Default
The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 40 indicates the lowest priority.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 16-1.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1.
When the instruction code in FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
−
−
Note 1
INTAD
INTRTC
INTRTCI
INTKR
INTST2
/INTCSI20
/INTIIC20
INTSR2
INTSRE2
INTTM04
INTTM05
INTTM06
INTTM07
INTP6
INTP7
INTP8
INTP9
INTP10
INTP11
BRK
RESET
POC
LVI
WDT
TRAP
Name
End of A/D conversion
Fixed-cycle signal of real-time counter/alarm
match detection
Interval signal detection of real-time counter
Key return signal detection
UART2 transmission transfer end or buffer
empty interrupt/CSI20 transfer end or buffer
empty interrupt/IIC20 transfer end
End of UART2 reception
End of timer channel 4 count or capture
End of timer channel 5 count or capture
End of timer channel 6 count or capture
End of timer channel 7 count or capture
Pin input edge detection
Execution of BRK instruction
RESET pin input
Power-on-clear
Low-voltage detection
Overflow of watchdog timer
Execution of illegal instruction
UART2 reception error occurrence
Table 16-1. Interrupt Source List (2/2)
CHAPTER 16 INTERRUPT FUNCTIONS
Interrupt Source
User’s Manual U17893EJ8V0UD
Trigger
Note 3
Note 4
Internal
External
Internal
External
Internal/
External
−
−
Address
003CH
004CH
0034H
0036H
0038H
003AH
003EH
0040H
0042H
0044H
0046H
0048H
004AH
004EH
0050H
0052H
0054H
007EH
0000H
Vector
Table
Configuration
Type
Basic
(C)
(D)
(A)
(A)
(B)
−
Note 2
599